Solid-State Imaging Device Column Parallel AD Conversion Pixel Addition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing solid-state imaging devices face challenges in increasing pixel dynamic range and reducing power consumption, particularly in performing pixel addition without increasing circuit scale or power consumption.
Innovation Solution
A solid-state imaging device with a column parallel AD conversion system that includes a first and second switching unit, allowing for pixel signal accumulation and comparison with a ramp reference signal, enabling pixel addition by disconnecting and reconnecting pixel signal accumulating units to facilitate comparison between adjacent pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pixel addition is performed by using a common floating diffusion portion for adjacent pixels, then pixel addition is achieved, but the excess capacity of the FD portion cannot be added and pixel dynamic range cannot be increased
Solution Approach 1:
The pixel signal accumulating unit is divided into a first pixel signal accumulating unit and a second pixel signal accumulating unit. The first unit accumulates signals from first pixels, while the second unit accumulates signals from second pixels adjacent in the row direction. This segmentation allows independent accumulation paths that can be selectively combined to achieve pixel addition while maintaining the ability to expand dynamic range through the first unit's full capacity.
Solution Approach 2:
The invention transitions from vertical pixel addition (column direction) to horizontal pixel addition (row direction) by introducing a second pixel signal accumulating unit connected to second pixels adjacent in the row direction. This dimensional change allows the system to utilize the excess capacity of the first pixel signal accumulating unit for adding pixel signals from adjacent columns, thereby expanding dynamic range while performing pixel addition.
2Quantity of substance
If pixel addition processing is performed at a processing block after the up/down counter, then pixel addition is achieved, but power consumption of the ADC remains the same and does not reduce
Solution Approach 1:
The invention performs pixel addition in advance within the ADC circuit itself, before the up/down counter operation. By accumulating pixel signals from adjacent pixels in the second pixel signal accumulating unit and adding them to the first unit's accumulated signal, the addition is completed before the counting process. This preliminary action reduces the dynamic range requirement for subsequent processing stages, allowing the up/down counter to operate at higher speeds with reduced power consumption.
Solution Approach 2:
The second pixel signal accumulating unit acts as an intermediary structure that temporarily holds and accumulates pixel signals from second pixels. This intermediary unit enables the addition of pixel signals at an intermediate stage within the ADC circuit, facilitating power reduction by completing addition operations before the high-power counter operation, thereby decoupling the timing of addition from the counting process.
3Device complexity
If the capacitance element for removing DC components is used for pixel signal accumulation, then the circuit scale is reduced, but the pixel signal accumulating unit cannot perform pixel addition
Solution Approach 1:
The first pixel signal accumulating unit is designed to serve multiple functions: it accumulates pixel signals from first pixels during normal operation, and also accumulates pixel signals from second pixels during pixel addition mode. By making this unit universal, the circuit avoids adding separate accumulation structures, thereby maintaining compact circuit scale while enabling pixel addition capability through the integrated second pixel signal accumulating unit.
Solution Approach 2:
The invention merges the pixel signal accumulation function with the DC component removal function by using the first pixel signal accumulating unit to perform both roles. The unit accumulates pixel signals while inherently filtering DC components through its capacitance-based structure. This merging eliminates the need for separate DC removal circuits, reducing overall circuit scale while maintaining pixel addition capability through the combined first and second accumulating units.
4Productivity
If a column parallel ADC conversion scheme is used, then high frame rate and high resolution are achieved, but power consumption increases when performing pixel addition
Solution Approach 1:
The invention implements periodic switching between normal operation mode and pixel addition mode through the first and second switching units. During normal mode, the first pixel signal accumulating unit operates independently for high-speed frame rate capture. When pixel addition is required, the system periodically transitions to addition mode where the second pixel signal accumulating unit is activated and connected, allowing the ADC to perform addition operations in a periodic manner rather than continuously, thereby reducing average power consumption while maintaining high frame rate capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient pixel addition with reduced power consumption and expanded dynamic range, as the power consumption remains the same for both normal and pixel addition modes, and the structure enables faster processing without prolonging operation time.
Implementation Method 1
each including a photodiode 31A and a transfer transistor 32A
Data Source
AI summary
A solid-state imaging device and an imaging apparatus are provided. The solid-state imaging device performs an AD conversion in a column parallel for an analog pixel signal outputted from each of pixels disposed in a two-dimensional matrix shape. The solid-state imaging device includes: an AD conversion unit including a plurality of pixel signal accumulating units; a first switching unit for disconnecting parallel connection of a second pixel signal accumulating unit other than a first pixel signal accumulating unit which is one of the plurality of pixel signal accumulating units; and a second switching unit for connecting the second pixel signal accumulating unit to a pixel signal line of a second pixel adjacent to the first pixel in a row direction, when parallel connection of the second pixel signal accumulating unit is disconnected by the first switching unit.