Solid-State Imaging Device Rectifier Circuit Short Circuit Isolation
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Solution Overview
Problem
In solid-state imaging devices, a short circuit between the row selection line and readout line can cause abnormal output voltage values, affecting adjacent integration circuits and making it difficult to interpolate pixel values, potentially leading to widespread abnormality in output voltage values.
Innovation Solution
The device incorporates a sensor panel section with photodetectors and thin-film transistors on a first substrate and a readout circuit section on a second substrate, featuring panel-side connection points, rectifier circuits, and circuit elements with resistance components to manage potential differences and prevent abnormal voltage outputs. When a short circuit occurs, the rectifier circuit turns on, and the resistance component adjusts the potential to the constant potential line, isolating the affected column and preventing abnormal voltage propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a short circuit between row selection line and readout line occurs, then the potential of the readout line approaches that of the row selection line, but this causes abnormal output voltage values from integration circuits and may affect adjacent integration circuits
Solution Approach 1:
A constant potential line is introduced as an intermediary between the readout line and the integration circuit. This constant potential line acts as a mediator that maintains a stable potential at the input terminal of the integration circuit, preventing abnormal voltage propagation from the readout line while ensuring proper signal input to the integration circuit.
2Measurement precision
If the output voltage value from an integration circuit becomes abnormal, then pixel value interpolation can be performed for the affected column, but if multiple adjacent columns are affected, interpolation becomes difficult
Solution Approach 1:
The constant potential line is configured to prevent abnormal voltage propagation before it can affect multiple adjacent integration circuits. By establishing this protective mechanism in advance, the system proactively prevents the spread of abnormal voltages, ensuring that only isolated columns are affected and remain suitable for interpolation.
3Device complexity
If no protection mechanism is provided, then the device structure remains simple, but short circuits can cause widespread abnormality in output voltage values
Solution Approach 1:
The constant potential line is applied locally at the input terminal of each integration circuit, providing targeted protection only where needed. This localized approach prevents widespread abnormality without requiring a complete system redesign, maintaining overall structural simplicity while enhancing reliability at critical points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents output voltage abnormalities in other columns, reducing the impact of short circuits and maintaining accurate pixel value interpolation across the imaging device.
Implementation Method 1
a plurality of rectifier circuits respectively connected between a plurality of nodes, between the plurality of panel-side connection points and the plurality of integration circuits, and a constant potential line
Implementation Method 2
a plurality of circuit elements respectively connected between the plurality of nodes and the plurality of readout lines, and having resistance components
Implementation Method 3
A photodiode for converting light incident thereon into an electron is arranged in each pixel
Data Source
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AI summary
A solid-state imaging device 1A includes a sensor panel section 10 and a readout circuit section 40. The sensor panel section 10 is disposed on a glass substrate 12 and has a photodetecting section 20 including pixels P1,1 to PM,N arrayed in M rows and N columns, row selection lines Q1 to QM, and readout lines R1 to RN. The readout circuit section 40 is disposed on a substrate 41 and has N integration circuits 42. Rectifier circuits 72 are connected between nodes N1 to NN, between N panel-side connection points 13 and the integration circuits 42, and a constant potential line 71. Circuit elements 73 having resistance components are connected between the nodes N1 to NN and readout lines R1 to RN. Thus, even when a short circuit occurs between the row selection line and readout line at a certain column, output voltage values from the integration circuits at the other columns can be prevented from becoming abnormal.