Solid-State Imaging Device Shallow Trench Isolation Dark Current Prevention
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Solution Overview
Problem
Solid-state imaging devices using Shallow Trench Isolation (STI) face issues with thermal stress causing crystal defects, reduced photodiode area, and difficulty in preventing dark currents and white spots due to the challenges in forming a p+ area with sufficient impurity concentration and thermal diffusion.
Innovation Solution
The solution involves forming a relatively shallow p+ area and a deep p area with a thick oxide film on a substrate, using a gate insulation film only under the gate electrode of transistors, and implementing an impurity combination for gate electrode sections to prevent parasitic MOS transistor formation and ensure flat surface configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STI is used for element isolation with deeply-embedded silicon oxide film, then element isolation is achieved, but thermal stress causes crystal defects
Solution Approach 1:
The patent changes the depth parameter of the silicon oxide film embedding, transitioning from deep embedding to shallow embedding. This parameter change reduces the thermal expansion coefficient difference between the oxide film and silicon substrate, thereby reducing thermal stress and preventing crystal defects while maintaining effective element isolation.
2Reliability
If STI with deeply-embedded silicon oxide film is used, then element isolation is achieved, but photodiode area is reduced
Solution Approach 1:
The patent changes the spatial parameter of the isolation structure by reducing the embedding depth of the silicon oxide film. This creates more available area in the pixel region for the photodiode while maintaining sufficient isolation between elements through the shallow trench structure.
3Reliability
If p+ area is formed to prevent dark currents and white spots, then dark current prevention is improved, but manufacturing complexity increases due to difficulty in achieving sufficient impurity concentration
Solution Approach 1:
The patent changes the concentration parameter of the p-type impurity in the shallow trench isolation region. By optimizing the impurity concentration to be higher than the surrounding regions but achievable through standard manufacturing processes, the patent effectively prevents dark currents and white spots while maintaining ease of manufacture.
4Productivity
If element isolation area width is reduced, then pixel density is improved, but dark current prevention becomes more difficult
Solution Approach 1:
The patent uses a composite structure combining silicon oxide film and p-type impurity-doped regions in the shallow trench isolation. This composite approach provides effective dark current prevention through the p-type region even when the overall isolation area is minimized, enabling high pixel density while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the width of the element isolation area, increases the photodiode area, enhances sensitivity, and prevents dark currents and white spots, while maintaining surface flatness and simplifying the device structure.
Implementation Method 1
a pixel including a photoelectric conversion section, and a conversion section that converts an electric charge generated by photoelectric conversion into a pixel signal
Data Source
AI summary
An imaging device that includes a substrate, a photoelectric conversion section disposed in the substrate, an element isolation region disposed adjacent to the photoelectric conversion section, a floating diffusion electrically connected to the photoelectric conversion section, an amplification transistor having a gate electrode and an active region, and a contact section disposed on the gate electrode of the amplification transistor. The contact section overlaps the active region of the amplification transistor. The floating diffusion is electrically connected to the gate electrode of the amplification transistor via the contact section. The width of the gate electrode of the amplification transistor is larger than a width of the active region of the amplification transistor. The photoelectric conversion section includes a first type impurity, and the element isolation region includes a second type impurity having a conductivity opposite to the first type impurity.