Imaging Device Vertical Sync Adjustment for Latency Reduction
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Solution Overview
Problem
Existing technologies face challenges in synchronizing camera input and display output when they operate asynchronously, leading to unstable latency, increased storage requirements, and complex buffering processes, particularly with USB cameras that lack a shared clock.
Innovation Solution
An imaging device and information processing system that include a vertical synchronizing signal adjusting mechanism to synchronize frame data output with display output by monitoring shift times and adjusting the generation of the vertical synchronizing signal in pixel count units, eliminating the need for a synchronizing buffer and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronizing buffer is used to adjust output timing between camera and display, then timing synchronization is achieved, but latency increases and storage area is consumed
Solution Approach 1:
The patent extracts the synchronization function from the host terminal and relocates it to the imaging device itself. By having the imaging device autonomously adjust its vertical synchronizing signal timing based on feedback about timing shifts, the system eliminates the need for a synchronizing buffer in the host terminal, thereby reducing both latency and storage requirements while maintaining synchronization reliability
Solution Approach 2:
The patent implements a feedback mechanism where the host terminal monitors the timing shift between input frame data and reference timing, then sends adjustment instructions back to the imaging device. The imaging device uses this feedback to dynamically adjust its vertical synchronizing signal generation, creating a closed-loop system that maintains synchronization without requiring large buffers
2Reliability
If a synchronizing buffer is used to adjust output timing, then timing synchronization is achieved, but device complexity increases
Solution Approach 1:
The patent removes the complex synchronizing buffer mechanism from the host terminal and replaces it with simple timing monitoring and instruction transmission. The synchronization functionality is extracted and embedded in the imaging device, which already has the capability to generate and adjust synchronizing signals, thereby simplifying the overall system architecture
Solution Approach 2:
The imaging device performs self-adjustment of its synchronizing signal timing based on feedback from the host terminal. Rather than requiring the host terminal to manage complex buffering and timing adjustment, the imaging device serves itself by autonomously modifying its vertical synchronizing signal generation to match display timing requirements
Data Source
AI summary
A shift time monitoring section of a host terminal monitors a shift between the input timing of frame data from an imaging device and the ideal input timing for the frame data, the ideal input timing being obtained from the output frequency of a display. An operation cycle adjusting section transmits a request signal for adjusting the operation cycle per frame in the imaging device according to the magnitude of the shift in the input timing. An H-counter section of the imaging device counts the outputting of the horizontal synchronizing signal with a vertical synchronizing signal in the imaging device as a starting point, and generates a signal at a predetermined scanning line. A VSync adjusting counter section counts a pixel clock with the signal from the H-counter section as a starting point, and generates a vertical synchronization signal at a value set to the pixel clock.