Solid-State Imaging Device Tapered Insulating Layer
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Solution Overview
Problem
In solid-state imaging devices with a 3D structure, the presence of connection electrodes and material films on the light receiving surface can lead to a large distance between the light receiving surface and the on-chip lens, degrading light receiving characteristics.
Innovation Solution
The implementation of a tapered step portion in the insulating layer on the light receiving surface, which is gradually thinned from the connection unit region to the pixel region, reduces the distance between the on-chip lens and the light receiving surface, improving light focusing and sensitivity characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection electrodes and material films are provided on the light receiving surface for electrical connection, then electrical connectivity between sensor substrate and circuit substrate is achieved, but the distance between light receiving surface and on-chip lens increases, degrading light receiving characteristics
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture where the circuit substrate is bonded to the opposite surface of the sensor substrate. This vertical stacking allows connection electrodes to be positioned in the thickness direction rather than on the light receiving surface, maintaining electrical connectivity while preserving optical path clarity.
Solution Approach 2:
The imaging device is divided into functionally separate substrates: a sensor substrate for photoelectric conversion and a circuit substrate for signal processing. This segmentation allows each substrate to be optimized independently - the sensor substrate maintains a clear light receiving surface while the circuit substrate handles all electrical connections through bonded interfaces.
2Productivity
If a 3D structure with separate circuit substrate is used, then integration density and opening area are improved, but manufacturing complexity and bonding precision requirements increase
Solution Approach 1:
The bonding interface is designed with universal compatibility - both substrates are prepared with bonding pads and alignment marks that follow standardized patterns. This allows the same bonding process and equipment to be used for connecting different substrate types and sizes, reducing manufacturing complexity despite the 3D structure.
3Reliability
If wafer bonding is performed for substrate connection, then integration is achieved, but misalignment, distortion, and void formation may occur during bonding
Solution Approach 1:
Alignment marks are pre-formed on both substrates before bonding, and the substrates are pre-positioned and clamped in alignment fixtures. This preliminary alignment action ensures that when bonding occurs, the substrates are already correctly positioned, preventing misalignment and distortion during the bonding process.
Solution Approach 2:
A bonding pad layer is introduced as an intermediary between the two substrates. This intermediate layer accommodates slight dimensional variations and thermal expansion differences, acting as a buffer that prevents stress-induced distortion and void formation while maintaining reliable electrical and mechanical connection.
Data Source
AI summary
There is provided a solid-state imaging device including a sensor substrate having a sensor-side semiconductor layer including a pixel region in which a photoelectric conversion section is provided and a sensor-side wiring layer provided on an opposite surface side from a light receiving surface of the sensor-side semiconductor layer, a circuit substrate having a circuit-side semiconductor layer and a circuit-side wiring layer and provided on a side of the sensor-side wiring layer of the sensor substrate, a connection unit region in which a connection section is provided, the connection section having a first through electrode, a second through electrode, and a connection electrode connecting the first through electrode and the second through electrode, and an insulating layer having a step portion which has the connection electrode embedded therein and has a film thickness that gradually decreases from the connection unit region to the pixel region.


