Imaging Display Apparatus Frame Rate Synchronization via VRAM Buffering

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Solution Overview

Problem

Image sensors operating at low frame rates, such as 24 fps or 30 fps, face issues with image quality due to leakage current and flicker when combined with electronic view finders (EVFs) designed for high frame rates like 60 fps, leading to delays and unsynchronized operations.

Innovation Solution

An imaging display apparatus that stores image signals for one frame and displays them N times, with the display unit operating at a frame rate N times that of the imaging unit, ensuring synchronized operations and minimizing delays by controlling the timing of image signal output and vertical synchronizing signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the display unit operates at a high frame rate (60 fps) to reduce leakage current influence and achieve fine design, then image quality and device size are improved, but synchronization with low frame rate image sensors (24 fps or 30 fps) becomes difficult and displaying delay increases

Engineering Contradiction:
Improveimage qualityVSAvoiddisplaying delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The storage unit stores image signals in advance before they are needed for display. By pre-storing the image signals captured at low frame rates, the system prepares the data ahead of time, allowing the display unit to operate at high frame rates without experiencing delays or synchronization issues.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The storage unit acts as an intermediary between the image sensor and the display unit. It buffers the image signals, decoupling the timing requirements of the low frame rate sensor from the high frame rate display, thereby resolving the synchronization conflict and enabling both components to operate optimally.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the display unit operates at a low frame rate (30 fps) to synchronize with the image sensor, then synchronization is achieved, but leakage current influence increases and image quality deteriorates

Engineering Contradiction:
ImprovesynchronizationVSAvoidleakage current influence
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Image signals are stored in advance in the storage unit before being displayed. This preliminary storage allows the display unit to operate at high frame rates without waiting for real-time signal generation, thereby avoiding the harmful effects of leakage current while maintaining synchronization through the buffered signals.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the capacity of the signal holding capacitor is increased to stabilize operation at low frame rate, then operational stability is improved, but device size increases

Engineering Contradiction:
Improveoperational stabilityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The solution transitions from a temporal buffering approach (holding signals longer in capacitors) to a spatial buffering approach (storing signals in a storage unit). By moving the buffering function to a separate storage dimension, the system achieves operational stability without requiring large capacitors, thereby avoiding an increase in device size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The storage unit serves as an intermediary that provides the necessary buffering capacity without being part of the pixel structure. This separates the stability function from the imaging elements, allowing stable operation at low frame rates while maintaining fine design and small device size.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10477139B2Imaging display apparatus
Publication Date: 2019.11.12 SEIKO EPSON CORP
  • US10477139B2 patent drawing
  • US10477139B2 patent drawing
  • US10477139B2 patent drawing

AI summary

An imaging display apparatus includes an imaging unit that images a subject at a first frame rate and outputs an imaging signal, an image processing portion that generates an image signal based on the imaging signal, a VRAM that stores the image signal, and a display unit that performs displaying based on the image signal at a second frame rate which is equal to or greater than N (N is a natural number equal to or greater than 2) times the first frame rate. The VRAM stores the image signals for one frame to be displayed by the display unit. The display unit performs displaying N times based on the image signals for one frame.