Solid-State Imaging Device Driver Circuit Buffer Short-Circuit
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Solution Overview
Problem
Existing solid-state imaging devices require calibration to adjust delay times for each column, which is time-consuming and increases circuit complexity, and accuracy decreases if not recalibrated with temperature or voltage changes.
Innovation Solution
A solid-state imaging device with a matrix of pixels and control wires, where drive circuits include buffer elements in multiple stages and a first wire short-circuits output wires of buffer elements in at least two stages, reducing delay differences between columns without the need for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a column skew correction circuit that adjusts delay time for each column is provided, then temporal differences of the shutter are reduced, but calibration for each solid-state imaging device is required and circuit scale increases
Solution Approach 1:
Multiple drive circuits sharing common buffer elements and control wires are merged to reduce the overall circuit scale. By having drive circuits share buffer elements connected through control wires, the patent reduces redundant components while maintaining the ability to control shutter timing for multiple columns simultaneously.
Solution Approach 2:
Buffer elements are designed to serve multiple functions across different drive circuits. The same buffer elements can be controlled by different drive circuits through control wires, allowing a single buffer element to serve multiple columns and reducing the total number of buffer elements needed.
2Measurement precision
If delay time adjustment for each column is implemented, then measurement accuracy is improved, but calibration time and steps increase
Solution Approach 1:
The patent changes the approach from individual column delay adjustment to group-based delay control. By controlling multiple columns through shared buffer elements and using control wires to distribute timing signals, the system achieves delay adjustment without requiring individual calibration for each column.
Solution Approach 2:
The drive circuits and buffer elements are designed to automatically synchronize timing through their interconnected structure. The shared buffer elements and control wire architecture enable automatic delay matching across columns without external calibration intervention.
3Manufacturing precision
If calibration is performed for each column, then delay time accuracy is maintained, but the process requires feedback and multiple steps
Solution Approach 1:
Control wires act as intermediaries between drive circuits and buffer elements, enabling centralized timing control. The control wires distribute timing signals and delay adjustments across multiple columns simultaneously, eliminating the need for individual calibration feedback loops for each column.
Solution Approach 2:
The patent segments the control architecture into drive circuits, control wires, and buffer elements that can be independently designed and optimized. This segmentation allows the system to achieve precise delay control through the coordinated operation of segmented components rather than through complex calibration of integrated circuits.
4Device complexity
If delay time is not adjusted, then circuit complexity is reduced, but delay differences between columns decrease measurement accuracy
Solution Approach 1:
The shared buffer elements and control wire architecture creates equipotential timing conditions across multiple columns. By connecting buffer elements through control wires that distribute timing signals uniformly, the system achieves equal delay characteristics across columns without requiring individual adjustment circuits.
Data Source
AI summary
A solid-state imaging device includes: pixels disposed in a matrix of pixel rows and pixel columns; control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; drive circuits that are provided for the control wires, each include buffer elements in at least two stages, and each output a control signal to one of the control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.