Imaging Device Electrode Connection Region Vertical Overlap
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Solution Overview
Problem
In imaging devices, there is a challenge to minimize chip area while enhancing the adhesion between the upper electrode and the photoelectric conversion layer, as well as between the photoelectric conversion layer and the lower electrodes, particularly when using materials with weak adhesion properties.
Innovation Solution
The imaging device design includes a semiconductor substrate with a pixel region and a peripheral region, covered by an insulating layer, where the upper electrode extends over the peripheral region, including a connection region that overlaps the circuitry, allowing for increased coverage of the photoelectric conversion layer and electrodes, thereby reducing chip area and improving adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the connection region is arranged between the pixel region and pad as in conventional technology, then the electrical connection between upper electrode and connection electrodes is achieved, but the chip area increases
Solution Approach 1:
The connection region is repositioned from a linear arrangement (between pixel region and pad) to a vertical overlap arrangement (above the peripheral region). This dimensional change allows the second electrode to extend above the peripheral region and connect to the third electrode through the analog circuitry layer, achieving electrical connection while utilizing the vertical space above existing components rather than consuming additional horizontal chip area.
2Strength
If the upper electrode coverage is increased to enhance adhesion, then the adhesion between upper electrode and photoelectric conversion layer is improved, but the chip area increases
Solution Approach 1:
The second electrode is designed to serve multiple functions: it acts as the upper electrode for photoelectric conversion in the pixel region, extends above the peripheral region to form a connection region, and provides adhesion enhancement coverage. This multi-functional design allows the same electrode structure to achieve both photoelectric conversion and adhesion enhancement without requiring additional separate structures that would increase chip area.
Solution Approach 2:
The electrode coverage is extended into the vertical dimension by having the second electrode extend above the peripheral region. This allows the connection region to overlap with the analog circuitry in the vertical stack, achieving adhesion enhancement through increased coverage area without consuming additional horizontal chip area.
3Area of stationary object
If the connection region overlaps the analog circuitry, then the chip area is minimized, but noise interference to the analog circuitry may increase
Solution Approach 1:
The connection region is nested above the analog circuitry in the vertical stack, with the second electrode forming the connection region that overlaps the analog circuitry. This nesting arrangement allows the connection function to be achieved within the vertical space above the analog circuitry without requiring additional horizontal area, while the digital circuitry layer provides noise shielding.
Solution Approach 2:
The digital circuitry layer acts as an intermediary or shield between the connection region and the analog circuitry. By positioning the digital circuitry between the connection region (second electrode) and the analog circuitry, the patent uses the digital circuitry as a noise barrier to protect the sensitive analog signals from electromagnetic interference generated by the connection region.
Data Source
AI summary
An imaging device including a semiconductor substrate including a pixel region and a peripheral region; an insulating layer covering the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer covering the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry electrically connected to the first electrodes; peripheral circuitry electrically connected to the detection circuitry, and; and a third electrode located on the insulating layer. The second electrode includes a connection region in which the second electrode is connected to third electrode, the connection region overlaps analog circuitry in a plan view, and in any cross-sections perpendicular to a surface of the semiconductor substrate and parallel to a column or row direction and that intersects at least one of the first electrodes, the digital circuitry includes no transistor that is located directly below the connection region.