Solid-State Imaging Element With Back-Side Wiring for Crosstalk Reduction

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Solution Overview

Problem

The stacking of semiconductor substrates in existing solid-state imaging elements leads to crosstalk and noise issues due to the proximity of wiring lines connecting the semiconductor substrates with the pixel circuit.

Innovation Solution

A solid-state imaging element design where the first and second semiconductor substrates are joined such that their circuits face the pixel substrate, with connections made on the opposite side, using Through Silicon Vias (TSVs) and a redistribution layer to separate wiring lines, reducing crosstalk and noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If semiconductor substrates are stacked with wiring lines connecting the substrates close to the pixel circuit, then the device complexity is reduced and manufacturing is simplified, but crosstalk and noise occur in the pixel circuit

Engineering Contradiction:
Improvestacking structureVSAvoidcrosstalk and noise
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dimensional separation by moving the wiring lines connecting semiconductor substrates to the back surface side of the pixel substrate, away from the front surface pixel circuit. This spatial reconfiguration in the third dimension (depth/stacking direction) eliminates crosstalk while maintaining the simplified stacking structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the wiring lines into two distinct groups: those on the front surface connecting to pixel circuits, and those on the back surface connecting semiconductor substrates. This segmentation separates the signal paths to prevent interference while maintaining functional connectivity.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If wiring lines are placed close to pixel circuits for compact layout, then the area is reduced, but noise interference increases in the pixel circuit

Engineering Contradiction:
Improvesubstrate areaVSAvoidnoise interference
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent utilizes the back surface of the pixel substrate as an additional dimension for routing wiring lines. This allows compact front surface layout for pixel circuits while accommodating substrate connection wiring on the back surface, eliminating noise interference without increasing overall area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Object-affected harmful factors

If wiring lines are separated to reduce crosstalk, then the manufacturing precision requirement increases, but the crosstalk is suppressed

Engineering Contradiction:
Improvecrosstalk suppressionVSAvoidwiring line positioning
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent achieves automatic spatial separation by routing wiring lines through different surfaces (front vs. back) of the pixel substrate. This dimensional approach provides inherent crosstalk suppression without requiring extremely precise lateral positioning, as the vertical separation is built into the substrate structure itself.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12389702B2Solid-state imaging element
Publication Date: 2025.08.12 SONY SEMICON SOLUTIONS CORP
  • US12389702B2 patent drawing
  • US12389702B2 patent drawing
  • US12389702B2 patent drawing

AI summary

A solid-state imaging element includes a first semiconductor substrate having a first semiconductor circuit on a first surface of the substrate, a second semiconductor substrate having a second semiconductor circuit on a second surface of the substrate, and a pixel substrate having a pixel circuit on one surface of the substrate, in which the first semiconductor substrate, the second semiconductor substrate, and the pixel substrate are joined to each other such that the first surface of the first semiconductor substrate and the second surface of the second semiconductor substrate face the one surface of the pixel substrate, and the first semiconductor circuit and the second semiconductor circuit are connected to each other on the first surface side and the second surface side, opposite to the side facing the pixel substrate.