Solid-State Imaging Element Pixel Data Transfer Reduction
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Solution Overview
Problem
In solid-state imaging elements, the increasing number of pixels leads to higher power consumption due to the repeated transfer of reset and signal levels for correlated double sampling (CDS) processing, which is inefficient.
Innovation Solution
Implementing a solid-state imaging element with storage units that hold reset and signal data and an arithmetic circuit to calculate the difference before transfer, allowing for shared arithmetic operations and reduced data transfer, including bit-by-bit or unit-of-two-bit processing, and arranging arithmetic circuits in a two-dimensional lattice manner for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the repeater transfers both reset level and signal level to the CDS circuit for each pixel, then CDS processing can be performed to remove fixed pattern noise, but the number of transfers increases and power consumption increases as the number of pixels increases
Solution Approach 1:
The arithmetic circuit performs the subtraction operation between reset data and signal data before the data is transferred to the CDS circuit. By completing the arithmetic operation in advance within the storage unit, the system eliminates the need for repeated transfers of both reset and signal levels, thereby reducing power consumption while maintaining image quality through CDS processing
Solution Approach 2:
The invention extracts the arithmetic operation function from the external CDS circuit and places it within the storage unit. This extraction allows the storage unit to independently perform the subtraction operation locally, eliminating the need for repeated data transfers to an external CDS circuit and thus reducing power consumption
2Reliability
If the repeater transfers both reset level and signal level to the CDS circuit for each pixel, then CDS processing can be performed, but the number of transfers increases as the number of pixels increases
Solution Approach 1:
The arithmetic circuit performs the subtraction operation between reset data and signal data before the data is transferred to the CDS circuit. By completing the arithmetic operation in advance within the storage unit, the system eliminates the need for repeated transfers of both reset and signal levels, thereby reducing power consumption while maintaining image quality through CDS processing
Solution Approach 2:
The invention merges the arithmetic operation function with the storage unit, combining data holding and data processing functions in one location. This integration allows the system to perform CDS processing without requiring separate transfer operations for both reset and signal levels, improving transfer efficiency
3Speed
If multiple arithmetic circuits are arranged in a two-dimensional lattice manner for parallel processing, then processing speed increases, but device complexity increases
Solution Approach 1:
The invention divides the imaging device into multiple storage units arranged in a two-dimensional lattice, with each storage unit containing an arithmetic circuit. This segmentation allows parallel processing across multiple units while maintaining a regular, systematic structure that manages complexity through modular repetition
Data Source
AI summary
In a solid-state imaging element that transfers data in a vertical direction, the number of times of transfer is reduced. The solid-state imaging element is provided with a plurality of storage units and a data transfer circuit. In the solid-state imaging element, each of the plurality of storage units is provided with a holding unit that holds predetermined reset data and signal data according to an amount of light, and an arithmetic circuit that obtains a difference between the reset data and the signal data to output as pixel data. Furthermore, the data transfer circuit in the solid-state imaging element transfers the output pixel data.