Imaging Device Inspection Circuit Shared Memory Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing imaging devices with multiple memory units of different features, such as column memory and SRAM, require separate inspection circuits due to their distinct writing capabilities, leading to increased circuit area and complexity.
Innovation Solution
An imaging device with a control circuit that operates in different modes to inspect both types of memory units, allowing for shared inspection resources by designating addresses in a manner that aligns output values between the column memory and SRAM, reducing the circuit area needed for inspection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate inspection circuits are used for column memory and SRAM, then inspection accuracy is improved, but circuit area increases
Solution Approach 1:
The inspection circuit is designed to perform multiple functions by supporting both column memory inspection mode and SRAM inspection mode. The control circuit can switch between different operation modes (first operation mode for column memory, second operation mode for SRAM) to inspect different memory types using the same circuit infrastructure, thereby eliminating the need for separate inspection circuits.
Solution Approach 2:
The inspection circuit utilizes parameter changes in the inspection patterns to accommodate different memory types. By modifying the inspection pattern parameters (such as address designation sequences and timing) based on the target memory type, the same circuit can accurately inspect both column memory and SRAM without requiring separate dedicated circuits.
2Reliability
If separate inspection circuits are used for column memory and SRAM, then inspection reliability is improved, but device complexity increases
Solution Approach 1:
The inspection circuit is designed to perform multiple functions by supporting both column memory inspection mode and SRAM inspection mode. The control circuit can switch between different operation modes (first operation mode for column memory, second operation mode for SRAM) to inspect different memory types using the same circuit infrastructure, thereby eliminating the need for separate inspection circuits.
Solution Approach 2:
The inspection circuit employs dynamic operation modes that can be switched based on the inspection target. The control circuit dynamically adjusts the inspection pattern and timing parameters according to whether column memory or SRAM is being inspected, allowing a single circuit to adaptively handle different memory types with their distinct characteristics.
3Area of stationary object
If a shared inspection circuit is used for both memory types, then circuit area is reduced, but inspection accuracy deteriorates
Solution Approach 1:
The inspection circuit utilizes parameter changes in the inspection patterns to accommodate different memory types. By modifying the inspection pattern parameters (such as address designation sequences and timing) based on the target memory type, the same circuit can accurately inspect both column memory and SRAM without requiring separate dedicated circuits.
Solution Approach 2:
The inspection circuit employs dynamic operation modes that can be switched based on the inspection target. The control circuit dynamically adjusts the inspection pattern and timing parameters according to whether column memory or SRAM is being inspected, allowing a single circuit to adaptively handle different memory types with their distinct characteristics.
4Device complexity
If a shared inspection circuit is used for both memory types, then device complexity is reduced, but inspection reliability deteriorates
Solution Approach 1:
The inspection circuit utilizes parameter changes in the inspection patterns to accommodate different memory types. By modifying the inspection pattern parameters (such as address designation sequences and timing) based on the target memory type, the same circuit can accurately inspect both column memory and SRAM without requiring separate dedicated circuits.
Solution Approach 2:
The inspection circuit employs dynamic operation modes that can be switched based on the inspection target. The control circuit dynamically adjusts the inspection pattern and timing parameters according to whether column memory or SRAM is being inspected, allowing a single circuit to adaptively handle different memory types with their distinct characteristics.
Data Source
AI summary
An imaging device includes a first memory configured to perform writing to multiple addresses thereof by designating the multiple addresses on address-by-address basis, a second memory configured to perform writing simultaneously to multiple address thereof, and a control circuit that controls readout of signals from the first memory and the second memory. The control circuit is configured to perform a first operation mode to sequentially designate the multiple addresses of the first memory and sequentially perform readout of signals from the multiple addresses of the first memory, and a second operation mode to sequentially designate the multiple addresses of the second memory and sequentially perform readout of signals from the multiple addresses of the second memory so that an output value from the second memory becomes the same as a value expected as an output value from the first memory in the first operation mode.