Solid-State Imaging Device Isolation Region Design
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Solution Overview
Problem
Conventional solid-state imaging devices face challenges in miniaturization due to increased leakage currents and reduced sensitivity caused by trench isolation defects, leading to decreased signal-to-noise ratio and transistor performance degradation.
Innovation Solution
A solid-state imaging device design where the isolation region has a wider gap in the gate width direction at the channel region than at the source/drain region, formed by implanting impurities, which reduces leakage currents and gate capacity, and improves alignment accuracy for miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If shallow trench isolation (STI) is used to form isolation regions, then leakage currents are reduced, but etching damage causes defects and interface states that increase leakage currents and degrade signal-to-noise ratio
Solution Approach 1:
The patent changes the fundamental parameter of isolation region formation from etching-based STI to diffusion-based isolation. By using thermal diffusion of impurities to create the isolation region, the method eliminates etching damage, interface states, and defects that plague STI processes, thereby improving signal-to-noise ratio while maintaining leakage current suppression
Solution Approach 2:
The patent replaces the mechanical/physical etching process with a chemical thermal diffusion process. Instead of using plasma or chemical etching to create trenches and fill them with oxide, the invention uses thermal diffusion to directly form the isolation region through impurity redistribution, eliminating the harmful effects of etching
2Productivity
If pixels are miniaturized to increase resolution, then the number of pixels increases, but the amount of saturated signals and aperture ratio decrease, reducing sensitivity
Solution Approach 1:
The patent introduces a porous silicon oxide film in the isolation region that can selectively absorb excess carriers (holes) while maintaining electrical isolation. This porous structure provides additional charge storage capacity that compensates for the reduced signal charge in miniaturized pixels, thereby maintaining sensitivity despite smaller pixel sizes
Solution Approach 2:
The porous silicon oxide film acts as an intermediary that absorbs excess holes and prevents them from reaching the photo diode, thereby reducing noise. This mediator structure allows the system to maintain high sensitivity even as pixel size decreases and signal charge reduces
3Ease of manufacture
If isolation region is formed by STI to reduce capacitance, then conversion efficiency improves, but leakage currents increase due to defects in the isolation region
Solution Approach 1:
The patent changes the formation mechanism from STI (etching + oxidation) to thermal diffusion, fundamentally altering how the isolation region is created. This parameter change eliminates the defects that cause leakage currents while maintaining the capacitance reduction benefit through proper diffusion profile control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances sensitivity by reducing noise and transistor performance variations, facilitating pixel miniaturization while maintaining image quality.
Implementation Method 1
the other portion of the isolation region, which is not in contact with the FD, is a p-type diffusion isolation region
Implementation Method 2
a photoelectric conversion film photoelectrically converts the light to generate a charge
Implementation Method 3
an impurity region of a second conductivity type forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter
Data Source
AI summary
Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.