Solid State Imaging Device Isolation Diffusion Layer Layout
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Solution Overview
Problem
Miniaturization of MOS-type solid state imaging devices leads to charge leakage between pixels, causing color mixing and blooming, especially with long wavelength light, due to the narrowing of insulating isolation parts and instability in amplifier transistors during high-speed operation.
Innovation Solution
A solid state imaging device with a specific layout and diffusion layer structure, where a second conductivity type isolation diffusion layer is formed below the insulating isolation part, wider than the first, to prevent charge leakage and enhance sensitivity, and the amplifier transistor is formed in a high concentration well region to stabilize operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the insulating isolation part is narrowed to miniaturize pixels, then pixel density and resolution are improved, but charge leakage to adjacent pixels increases causing color mixing and blooming
Solution Approach 1:
The patent extends the isolation diffusion layer from a single shallow layer to a multi-layer structure with different depths. The first isolation diffusion layer is formed at a shallow depth, while the second isolation diffusion layer is formed at a deeper depth in the substrate. This vertical dimensionality change allows the isolation structure to effectively block charge leakage paths that extend deep into the substrate, thereby preventing color mixing and blooming even when the insulating isolation part is narrowed for pixel miniaturization.
Solution Approach 2:
The patent implements a nested structure where the second isolation diffusion layer is positioned beneath the first isolation diffusion layer. The source/drain region of the amplifier transistor is formed within the first isolation diffusion layer, while the second isolation diffusion layer provides an additional isolation barrier below it. This nested arrangement creates multiple levels of charge blocking, effectively preventing charge leakage to adjacent pixels while maintaining narrow insulating isolation parts for high resolution.
2Reliability
If the amplifier transistor is formed in a high concentration well region to stabilize operation during high-speed imaging, then operational stability is improved, but device complexity increases
Solution Approach 1:
The patent combines the formation of the high concentration well region with the isolation diffusion layer structure. The second isolation diffusion layer is formed to extend beneath the amplifier transistor region, and the high concentration well is integrated into this existing structure. This merging approach provides the necessary potential well for stable high-speed operation while utilizing the same fabrication processes and structural framework, thereby minimizing additional device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves high resolution and sensitivity without color mixing or blooming, even when miniaturized, by preventing charge leakage and ensuring stable operation of amplifier transistors.
Implementation Method 1
charges produced by photoelectric conversion of the photoelectric conversion element 101
Data Source
AI summary
Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.