Solid-State Imaging Element Memory Optimization via Correlated Double Sampling

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Solution Overview

Problem

The increase in memory capacity with the number of sampling times in solid-state imaging elements performing correlated double sampling processing leads to higher costs and increased mounting area, necessitating a reduction in memory capacity.

Innovation Solution

A solid-state imaging element that includes a pixel circuit generating reset and signal levels, an analog-to-digital converter converting these levels into digital data, and an arithmetic circuit that calculates and holds the difference between reset and signal data, optimizing memory capacity by summing the base-2 logarithm of the number of signal levels and exposure times, and using stacked semiconductor substrates for efficient data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of sampling times is increased to improve correlated double sampling processing, then the sampling accuracy is improved, but the memory capacity increases

Engineering Contradiction:
Improvesampling accuracyVSAvoidmemory capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent divides the sampling process into multiple stages, where only the necessary data from each sampling operation is stored in the memory. Instead of storing all N samples simultaneously requiring N×B bits, the system processes and stores only the essential difference information, segmenting the data storage requirement to minimize memory capacity while maintaining sampling accuracy.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If the memory capacity is reduced to decrease cost and mounting area, then the manufacturing cost is reduced, but the ability to perform multiple sampling operations is limited

Engineering Contradiction:
Improvemanufacturing costVSAvoidmultiple sampling capability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent performs preliminary processing of the sampled data by calculating the difference between the reset level and signal level immediately after sampling. This preliminary action of computing the difference allows the system to store only the essential result rather than the raw sampled data, enabling multiple sampling operations to be performed with minimal memory capacity while maintaining full functionality.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11039099B2Solid-state imaging element, solid-state imaging apparatus, and method for controlling solid-state imaging element
Publication Date: 2021.06.15 SONY SEMICON SOLUTIONS CORP
  • US11039099B2 patent drawing
  • US11039099B2 patent drawing
  • US11039099B2 patent drawing

AI summary

An increase in memory capacity is suppressed in a solid-state imaging element that performs correlated double sampling processing. A pixel circuit sequentially generates each of a predetermined reset level and a plurality of signal levels corresponding to the exposure amount. An analog-to-digital converter converts a predetermined reset level into digital data and outputs the data as reset data, converts each of the plurality of pieces of signal data into digital data, and outputs the data as signal data. An arithmetic circuit holds a difference between the reset data and the signal data output first, as held data in a memory, and then adds the held data and the signal data output second and subsequent times together and causes the memory to hold the added data as new held data.