Solid-State Imaging Device Parallel Charge Transfer
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Solution Overview
Problem
In two-dimensional flat-panel image sensors with amorphous silicon photodiodes, increasing frame rate leads to charges not being fully transferred within the predetermined time, causing a delay effect where image data from one frame is superimposed on the next, resulting in image lag and variations in output characteristics due to parallel holding circuits having different output characteristics.
Innovation Solution
The solid-state imaging device performs operations in parallel, allowing charges from one row to be integrated and output sequentially through second holding circuits while simultaneously inputting charges from another row to integration circuits, extending the charge input time and reducing photodiode charges, thus addressing the delay effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frame rate is increased in a two-dimensional flat-panel image sensor, then the imaging speed is improved, but charges are not entirely transferred within the predetermined transfer time, causing a delay effect where charges from one frame are superimposed on the next frame
Solution Approach 1:
The image sensor is divided into multiple independent pixel units, each with its own photoelectric conversion element and signal processing circuit. This segmentation allows parallel processing of charges from different regions, enabling complete charge transfer even at high frame rates by processing multiple segments simultaneously rather than sequentially
Solution Approach 2:
The patent implements preliminary charge transfer operations before the vertical transfer period begins. By initiating charge transfer in advance and using holding circuits to temporarily store charges, the system ensures that all charges are completely transferred before the next frame integration starts, preventing the delay effect even at increased frame rates
2Productivity
If parallel holding circuits are provided to suppress delay in image readout time, then the readout speed is improved, but variations in output characteristics occur because different holding circuits have different output characteristics
Solution Approach 1:
The patent merges the output signals from multiple parallel holding circuits through a summing circuit that adds together the outputs. This combining approach ensures that all holding circuits contribute to a single unified output signal, eliminating variations caused by individual holding circuit characteristics while maintaining the high readout speed enabled by parallel operation
Solution Approach 2:
The patent implements feedback mechanisms where the output characteristics of holding circuits are monitored and adjusted. By using feedback to equalize the output levels of different holding circuits, the system maintains uniform output characteristics across all parallel circuits, ensuring consistent signal quality throughout the readout process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach suppresses variations in output characteristics and resolves the delay effect by ensuring complete charge transfer within the predetermined time, improving image quality and stability.
Implementation Method 1
MxN (each of M and N is an integer not less than 2) pixels each including a photodiode that are arrayed two-dimensionally in M rows and N columns
Data Source
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AI summary
A controlling section 6, by bringing readout switches SW1 of respective pixels Pm,n that compose a certain row out of the M rows into a connected state, causes charges generated in the row to be input to integration circuits Sn, causes first holding circuits HO1,n to hold voltage values output from the integration circuits Sn, and then brings transfer switches SW32 into a connected state to transfer the voltage values to the second holding circuits HO2,n, and thereafter performs in parallel an operation for causing the voltage values to be sequentially output from the second holding circuits HO2,n and an operation for, by bringing readout switches SW1 of respective pixels Pm+1,n that compose another row out of the M rows into a connected state, causing charges generated in the row to be input to the integration circuits Sn. Accordingly, a solid-state imaging device and a method of driving a solid-state imaging device capable of suppressing variations in output characteristics, while solving the problem due to a delay effect are realized.