Solid-State Imaging Pixel Array Orientation for Signal Delay Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Large-area solid-state imaging apparatuses face signal delay issues due to parasitic resistance and capacitance in signal lines, which limit driving frequency, and existing technologies do not address this problem effectively.
Innovation Solution
The solid-state imaging apparatus is designed with a pixel array arranged in rows and columns, featuring vertical and horizontal signal lines, scanning circuits, and a specific arrangement of shift registers to reduce signal delay by optimizing the length of signal lines, where the row direction is shorter than the column direction, thereby minimizing parasitic capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the chip area is increased to form a large-area solid-state imaging apparatus, then the imaging area is improved, but the signal delay caused by parasitic resistance and capacitance increases, limiting the driving frequency
Solution Approach 1:
The patent reorients the pixel array such that the shorter dimension corresponds to the row direction and the longer dimension to the column direction. This dimensional arrangement optimizes signal line lengths by configuring the pixel array orientation to minimize parasitic effects in the dominant signal transmission path, thereby maintaining higher driving frequencies despite large imaging area.
Solution Approach 2:
The patent changes the geometric parameters of the pixel array arrangement by specifying that the length in the row direction be smaller than the length in the column direction. This parameter optimization reduces the effective signal line length and parasitic capacitance, allowing large-area chips to operate at higher driving frequencies.
2Area of stationary object
If the chip area is increased, then the imaging area is improved, but the signal line length increases causing greater parasitic resistance and capacitance
Solution Approach 1:
The patent addresses signal line length by changing the dimensional orientation of the pixel array, configuring rows along the shorter dimension and columns along the longer dimension. This arrangement minimizes the length of horizontal signal lines that traverse the chip, reducing parasitic resistance and capacitance despite the large overall chip area.
Solution Approach 2:
The patent optimizes the geometric parameters of the pixel array by establishing that the row direction length be smaller than the column direction length. This parameter change reduces the maximum signal line length across the chip, thereby decreasing parasitic effects while maintaining large imaging area.
3Productivity
If the driving frequency is increased to improve frame rate, then the imaging efficiency is improved, but the signal delay becomes more significant
Solution Approach 1:
The patent reduces signal delay by changing the geometric parameters of the pixel array arrangement, specifically making the row direction length smaller than the column direction length. This parameter optimization shortens signal line lengths and reduces parasitic effects, enabling higher driving frequencies and frame rates without excessive signal delay.
Data Source
AI summary
An imaging apparatus has an imaging area formed by arranging a plurality of imaging blocks each including a pixel array, a plurality of vertical signal lines, a horizontal output line commonly provided for the plurality of vertical signal lines to read out signals read out to the plurality of vertical signal lines, a first scanning circuit, and a second scanning circuit, wherein signals of the pixels of a selected row in the pixel array are read out to the plurality of vertical signal lines in accordance with a driving pulse from the first scanning circuit, the signals read out to the plurality of vertical signal lines are sequentially read out to the horizontal output line in accordance with a driving pulse from the second scanning circuit, and a length in a row direction of the pixel array is smaller than a length in a column direction of the pixel array.