Solid-State Imaging Pixel Banks for High Speed Sensitivity
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Solution Overview
Problem
In solid-state imaging devices, increasing the number of pixels leads to longer common wires and higher wiring capacity, causing charge distribution and voltage decrease at the signal processing circuit input, making it difficult to simultaneously enhance imaging speed and sensitivity.
Innovation Solution
The device employs two holding circuits per pixel section, with one holding an initial noise voltage and the other a signal voltage, and transimpedance circuits to output pulse currents corresponding to charge quantities, which are then processed by integrating circuits to remove noise and maintain high imaging speed and sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of pixels is increased, then the imaging coverage is improved, but the common wire length increases causing voltage decrease and imaging speed deterioration
Solution Approach 1:
The pixel array is divided into multiple banks, with each bank having its own dedicated readout circuitry. This segmentation allows parallel processing of signals from different regions, reducing the effective wire length and capacitance for each processing channel while maintaining comprehensive imaging coverage across the entire sensor array.
Solution Approach 2:
The patent introduces a bank dimension to organize pixel sections, transforming the problem from a single long common wire to multiple shorter common wires arranged in a two-dimensional bank structure. This dimensional reorganization reduces the maximum wire length and associated capacitance while preserving the ability to capture across the full imaging area.
2Area of stationary object
If the common wire length is increased to accommodate more pixels, then the imaging coverage is improved, but the wiring capacity increases causing charge distribution and voltage decrease
Solution Approach 1:
The sensor is divided into multiple independent banks, each with dedicated readout circuits. This segmentation reduces the common wire length and total capacitance for each processing channel, preventing charge distribution effects and maintaining stable voltage levels at the input of signal processing circuits while still providing comprehensive imaging coverage through the combined output of all banks.
3Measurement precision
If the junction capacitance of photodiodes is high, then the light sensitivity is improved, but the imaging speed cannot be increased due to RC time constant limitations
Solution Approach 1:
By dividing the pixel array into multiple banks with dedicated readout circuits, the patent reduces the total capacitance that each readout circuit must handle. This segmentation allows the use of photodiodes with higher individual junction capacitance for improved sensitivity, while the distributed architecture prevents RC time constant limitations from bottlenecking the overall imaging speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased imaging speed and sensitivity by maintaining voltage levels at the signal processing circuit input, even with high junction capacitances, without needing to increase signal processing gain, thus preventing deterioration of imaging speed.
Implementation Method 1
a photodiode which generates charges corresponding to the intensity of incident light
Data Source
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AI summary
A solid-state imaging device 1 includes N pixel sections 10i to 10N, transimpedance circuits 20a and 20b, integrating circuits 30a and 30b, and a difference arithmetic circuit 40. Each pixel section 10n includes a photoelectric converting circuit including a photodiode, and a first holding circuit and a second holding circuit which hold an output voltage of the photoelectric converting circuit. A voltage held by the first holding circuit of each pixel section 10n is input into the difference arithmetic circuit 40 through a common wire 50a, the transimpedance circuit 20a, and the integrating circuit 30a. A voltage held by the second holding circuit of each pixel section 10n is input into the difference arithmetic circuit 40 through a common wire 50b, the transimpedance circuit 20b, and the integrating circuit 30b. A voltage corresponding to a difference between the voltages output from the integrating circuits 30a and 30b, respectively, is output from the difference arithmetic circuit 40.