Solid-State Imaging Pixel Transistors Tuned by Fin Channel Width
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Solution Overview
Problem
The miniaturization of pixels in solid-state imaging elements leads to a trade-off between transistor characteristic adjustment and manufacturing cost, as impurities introduced for transistor adjustment can diffuse between adjacent transistors, affecting their characteristics and increasing production costs.
Innovation Solution
A solid-state imaging element design featuring Fin-type transistors with channel regions of different widths and no impurity introduction, allowing for adjustment of threshold voltages through channel width variations, eliminating the need for impurity introduction processes and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If impurities are introduced into channel regions to adjust transistor characteristics, then transistor characteristic adjustment is achieved, but manufacturing cost increases and adjacent transistor performance is affected by impurity diffusion
Solution Approach 1:
The patent changes the geometric parameter (channel width) of the Fin-type transistor channel regions to adjust transistor characteristics. By varying the channel width between different transistor types (e.g., amplifier transistor vs. selection transistor), the threshold voltage and other characteristics are tuned without introducing impurities, thereby avoiding additional manufacturing steps and cost increases.
Solution Approach 2:
The patent applies local quality by creating channel regions with different widths in different locations to achieve different transistor characteristics. Each transistor type has specifically designed channel width dimensions tailored to its functional requirements, allowing precise characteristic adjustment without uniform impurity introduction across all transistors.
2Reliability
If impurities are introduced for transistor characteristic adjustment, then transistor performance is optimized, but impurity diffusion affects adjacent transistors and increases manufacturing complexity
Solution Approach 1:
The patent uses channel width as a design parameter to control transistor characteristics. By adjusting the channel width dimension during the Fin formation process, optimal transistor performance is achieved without additional impurity introduction steps, thereby simplifying the manufacturing process and reducing complexity.
Solution Approach 2:
The patent extracts the impurity introduction step from the transistor characteristic adjustment process. Instead of using impurity diffusion, the invention relies solely on geometric parameter adjustment (channel width variation), thereby removing the complex and problematic impurity introduction process from the manufacturing flow.
3Area of moving object
If pixel size is reduced for miniaturization, then pixel density increases, but impurity diffusion between adjacent transistors becomes more significant
Solution Approach 1:
The patent uses channel width parameter variation to maintain precise transistor characteristic control in miniaturized pixels. By locally adjusting channel width dimensions, the invention achieves accurate characteristic tuning without relying on impurity diffusion, which becomes problematic at smaller scales due to increased proximity between adjacent transistors.
Solution Approach 2:
The patent utilizes the vertical dimension by employing Fin-type transistors with channel regions extending in the thickness direction. This three-dimensional structure allows for precise control of transistor characteristics through channel width adjustment without being constrained by planar spacing, enabling pixel miniaturization while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables both the adjustment of transistor characteristics and pixel miniaturization without increasing manufacturing costs, while reducing random noise and maintaining transistor performance, thus improving image quality.
Implementation Method 1
a photoelectric conversion section configured to convert light into an electric charge
Data Source
AI summary
To provide an imaging element capable of adjusting characteristics of a pixel transistor and miniaturizing the pixel transistor.A solid-state imaging element is a solid-state imaging element including a plurality of pixels provided on a surface of a substrate, each of the pixels including: a photoelectric conversion section; a first transistor having one end connected to the photoelectric conversion section; a second transistor provided between a first power supply and a first signal line; and a third transistor connected between the second transistor and the first signal line. The second transistor includes a first channel region extending in a direction substantially perpendicular to the surface of the substrate, and a first gate electrode provided on an upper surface and both side surfaces of the first channel region and connected to another end of the first transistor. The third transistor has a second channel region extending in a direction substantially perpendicular to the surface of the substrate, and a second gate electrode provided on an upper surface and both side surfaces of the second channel region. A first width between both side surfaces of the first channel region and a second width between both side surfaces of the second channel region are different from each other.