Solid-State Imaging Device Pixel Isolation Crystal Orientation

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Solution Overview

Problem

The adoption of shallow trench isolation (STI) in solid-state imaging devices can induce stress near the interface, leading to dark current issues, while also reducing the effective open area of photodiodes and degrading sensitivity, especially when the crystal orientation of the STI is not optimized.

Innovation Solution

The crystal orientation of the sides of the photoelectric conversion section and element isolation section are aligned to match the orientation of the silicon substrate, reducing stress and allowing for a thinner high-density impurity buried layer, thereby maintaining high sensitivity and minimizing dark current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If STI is adopted as element isolation structure, then pixel unit size is reduced and sensitivity degradation is suppressed, but stress is induced near STI interface causing dark current

Engineering Contradiction:
Improvepixel unit sizeVSAvoiddark current
Core Design Contradiction:
Area of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent changes the crystal orientation parameter of the STI interface from conventional orientations to <110> orientation. This parameter change reduces stress concentration at the STI interface, thereby suppressing dark current generation while maintaining the benefits of STI isolation for pixel miniaturization

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent combines STI isolation structure with specifically oriented silicon substrate and high-density impurity layers. The composite structure of STI + oriented silicon + impurity layers works synergistically to reduce both stress-induced dark current and maintain electrical isolation effectiveness

Inventive Principle:
Principle #40Composite materials

2Object-affected harmful factors

If high-density impurity layer is formed at LOCOS interface, then dark current is reduced, but effective open area of photodiode is reduced and sensitivity degrades

Engineering Contradiction:
Improvedark currentVSAvoideffective open area
Core Design Contradiction:
Object-affected harmful factorsVSArea of moving object

Solution Approach 1:

The patent extracts the dark current suppression function from the LOCOS interface region by using STI isolation instead. This removes the need to form high-density impurity layers at the photodiode surface, thereby preserving the effective open area while still achieving dark current reduction through STI interface stress management

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces STI as an intermediary isolation structure that provides electrical isolation without requiring surface impurity layers. The STI acts as a mediator between the photodiode and isolation requirements, eliminating the trade-off between dark current suppression and open area maintenance

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces dark current and maintains high sensitivity even with miniaturized pixel units by optimizing the crystal orientation of the photoelectric conversion section and element isolation section, allowing for reduced stress and increased electron accumulation.

Implementation Method 1

a photoelectric conversion section constituting each of the pixel units is electrically isolated

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Implementation Method 2

it is feared that stress may be induced near the STI in a heat treatment process after formation of the STI and this may cause a dark current

Methodology Applied
Scientific EffectStress:

Data Source

PatentUS8035178B2Solid-state imaging device
Publication Date: 2011.10.11 GODO KAISHA IP BRIDGE 1
  • US8035178B2 patent drawing
  • US8035178B2 patent drawing
  • US8035178B2 patent drawing

AI summary

A plurality of pixel portions (12) are formed on a silicon substrate (11). A photoelectric converter portion (10) constituting each of the pixel portions (12) is electrically isolated by an element isolation portion (13) comprising an insulating film formed on the silicon substrate (11). The photoelectric converter portion (10) partitioned by the element isolation portion (13) is so formed that a crystal orientation of the sides in contact with the element isolation portion (13) corresponds to a &lt;00-1&gt; direction. This makes it possible to reduce dark current caused by stress in the vicinity of the interface of the element isolation portion (13) and maintain high sensitivity even if the pixel portions (12) are made smaller in size.