Solid-State Imaging Device Repeater Circuits Clock Transfer
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Solution Overview
Problem
In solid-state imaging devices with A/D conversion circuits of the SS+TDC type, the increased number of pixels leads to longer signal wiring for multiphase clocks, causing transfer delays and timing errors, which degrade the resolution of digital values output by each pixel.
Innovation Solution
The implementation of a solid-state imaging device with a pixel array unit, a ramp signal generation unit, and a clock generation unit, where repeater circuits are used to accurately transfer multiphase clocks to A/D conversion circuits, and power wiring is arranged to prevent interference with latch circuit power fluctuations, allowing for improved resolution and reduced signal wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of pixels in the pixel array unit is increased, then the imaging capability is improved, but the signal wiring length for multiphase clocks increases causing transfer delays and timing errors
Solution Approach 1:
The pixel array unit is divided into multiple blocks, with each block containing a subset of pixels and having its own dedicated A/D conversion circuit. This segmentation allows the clock generation unit to generate multiphase clocks for each block separately, reducing the signal wiring length within each block and minimizing transfer delays and timing errors, thereby maintaining high resolution despite the overall increase in pixel count.
Solution Approach 2:
A clock generation unit is introduced as an intermediary component that generates multiphase clocks specifically for each block of pixels. This intermediary ensures that each A/D conversion circuit receives accurately timed multiphase clocks with minimal transfer delay, preventing the degradation of resolution that would otherwise occur due to increased wiring length in large-scale pixel arrays.
2Reliability
If repeater circuits are added to transfer multiphase clocks accurately, then the transfer accuracy is improved, but the device complexity increases
Solution Approach 1:
Instead of adding repeater circuits throughout the entire pixel array, the system segments the pixel array into multiple blocks, each with its own A/D conversion circuit and dedicated multiphase clock routing. This segmentation eliminates the need for repeater circuits by ensuring that clock signal wiring length within each block remains short enough to maintain accuracy without additional buffering or repetition.
3Measurement precision
If power wiring is arranged to prevent interference with latch circuit power fluctuations, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The power wiring arrangement is optimized locally within each block by positioning power wirings for latch circuits in regions where they do not intersect with multiphase clock signal wirings. This local optimization prevents interference between power fluctuations and clock signals, ensuring accurate phase information transfer to the A/D conversion circuits without requiring complex global power distribution redesign.
Data Source
AI summary
A solid-state imaging device including: a pixel array unit in which a plurality of pixels outputting an analog pixel signal are arranged in a two-dimensional matrix form; a ramp signal generation unit configured to generate and output a ramp wave; a clock generation unit configured to generate and output multiphase clocks; and a signal-processing unit, wherein the signal-processing unit including: a plurality of analog-to-digital conversion circuits, and a plurality of repeater circuits, wherein each of the plurality of analog-to-digital conversion circuits includes: a comparison unit, and a latch unit, wherein each of the plurality of the analog-to-digital conversion circuits outputs the digital value according to the state of the phase held by each latch circuit, and wherein each of the plurality of the repeater circuits corresponding to the same set are arranged side by side, and the repeater circuits are connected in series.