Solid-State Imaging Device Sensitivity and Dynamic Range
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Solution Overview
Problem
Solid-state imaging devices face challenges in achieving high sensitivity and wide dynamic range, particularly in photoelectric-conversion-layer-stack-type devices that pull out holes as charges, due to differences in readout circuits compared to general photodiodes and the need for dynamic range enlargement.
Innovation Solution
A method of driving a solid-state imaging device is developed, where specific voltage relationships and threshold voltage ranges are established to ensure high sensitivity and wide dynamic range, involving formulas that govern the potentials of reset and output transistors, and the use of a photoelectric conversion layer with p-type and n-type organic semiconductors to enhance charge collection and transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If holes are used as charges for signal readout in photoelectric converter over silicon substrate, then sensitivity to G light is enhanced, but dynamic range is limited due to different readout circuit requirements
Solution Approach 1:
The patent changes the charge type parameter from holes to electrons for the photoelectric converter over silicon substrate, matching the charge type used in photodiodes within silicon substrate. This parameter change allows both pixel types to use the same n-channel MOS transistor readout circuit, enabling dynamic range enlargement through dual gain readout while maintaining high sensitivity to G light
2Measurement precision
If electrons are used as charges for signal readout in photodiode within silicon substrate, then sensitivity to B and R light is maintained, but dynamic range is limited by readout circuit design
Solution Approach 1:
The patent makes the readout circuit universal by using the same n-channel MOS transistor circuit for both photodiodes within silicon substrate and photoelectric converters over silicon substrate. This universality allows the circuit to handle different charge types (electrons from photodiodes, electrons from photoelectric converters) and implements dual gain readout capability, thereby enlarging the dynamic range while maintaining sensitivity
3Measurement precision
If different readout circuits are used for photodiodes and photoelectric converters, then specific sensitivity requirements are met, but device complexity increases
Solution Approach 1:
The patent employs a universal n-channel MOS transistor readout circuit that can process signals from both photodiodes within silicon substrate and photoelectric converters over silicon substrate. This single circuit design handles different charge types and implements dual gain functionality, reducing device complexity compared to using separate specialized circuits while maintaining the sensitivity requirements for different pixel types
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the solid-state imaging device to achieve high sensitivity and a wide dynamic range by optimizing charge accumulation and transport, preventing charge leakage and ensuring proper signal readout across varying light conditions.
Implementation Method 1
the light of 'G' (green) is detected by a photoelectric converter over the silicon substrate... holes among charges generated in a photoelectric conversion layer are accumulated in a pixel electrode
Implementation Method 2
a photoelectric conversion layer with p-type and n-type organic semiconductors to enhance charge collection and transport
Data Source
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AI summary
A solid-state imaging device includes a photoelectric conversion layer (107), a MOS transistor circuit. The photoelectric conversion layer (107) is formed over a semiconductor substrate (101). The MOS transistor circuit reads out a signal corresponding to charges generated in the photoelectric conversion layer (107) and then collected, and that is formed in the semiconductor substrate (101), the charges having a given polarity. The MOS transistor circuit includes a charge accumulation portion (104,FD), a reset transistor (204), and an output transistor (205). The charge accumulation portion (104,FD) is electrically connected with the photoelectric conversion layer (107). The reset transistor (204) resets a potential of the charge accumulation portion (104,FD) to a reset potential (Vs). The output transistor (205) outputs a signal corresponding to the potential of the charge accumulation portion (104,FD). The reset transistor (204) and the output transistor (205) have carriers whose polarity is opposite to the given polarity. In the MOS transistor circuit, following formula (1) is satisfied: GND < Vs < GND + ΔV2 + (Vdd/5) (1).