Imaging Sensor A/D Counter Code for Clock Skew Accuracy
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Solution Overview
Problem
In solid-state imaging apparatuses, significant clock signal skew leads to large errors in A/D conversion accuracy, degrading the resolution without increasing clock signal frequency.
Innovation Solution
The use of a counter code comprising low-order bit codes with phase-shifted clock signals and high-order bit codes based on gray codes, where the count value changes only the logical level of a 1-bit signal, minimizing errors even with significant skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple clock signals with different phases are used for low-order bit codes, then the resolution is improved, but clock signal skew causes large errors that degrade A/D conversion accuracy
Solution Approach 1:
The counter code is segmented into low-order bit codes (using multiple phase-shifted clock signals) and high-order bit codes (using gray codes). This segmentation allows the low-order bits to provide high resolution while the high-order gray code bits provide timing stability, resolving the contradiction between resolution and accuracy.
Solution Approach 2:
The counter code combines two different coding schemes (binary phase-coded signals for low-order bits and gray codes for high-order bits) into a composite structure. This composite approach leverages the advantages of both coding methods to achieve both high resolution and high accuracy simultaneously.
2Productivity
If the clock signal frequency is increased to improve resolution, then the conversion speed is improved, but clock signal skew increases causing larger errors
Solution Approach 1:
The invention changes the coding parameter from pure binary to a hybrid binary-gray code structure. This parameter change allows the system to maintain high conversion speed while using gray codes to minimize the impact of clock skew on accuracy, effectively decoupling speed and accuracy requirements.
3Reliability
If a binary code counter is used, then the count value varies synchronously with the clock signal, but incrementing changes multiple bits causing large errors under clock skew
Solution Approach 1:
Instead of using binary encoding where incrementing changes multiple bits, the invention inverts the approach by using gray code encoding where incrementing changes only one bit. This inversion of the encoding strategy fundamentally reduces the impact of clock skew on measurement accuracy.
Data Source
AI summary
There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.