Solid-state imaging device vertical shift register binning control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Solid-state imaging elements with photodetecting surfaces formed on monocrystalline silicon wafers are limited in size, and adding a circuit for vertical binning operations increases the size of the vertical shift register, making it difficult to achieve high integration, especially when formed on polycrystalline silicon films on insulating substrates.
Innovation Solution
A solid-state imaging device with a logic circuit that controls row selection wiring lines to enable both normal and vertical binning operations using a smaller vertical shift register, where shift register circuits are provided for every two row selection wiring lines, allowing for efficient charge output from multiple pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a circuit for vertical binning operation is added to the vertical shift register, then vertical binning operation is enabled, but the size of the vertical shift register increases
Solution Approach 1:
The patent merges the normal reading operation and vertical binning operation into a single unified vertical shift register structure. By using the same shift register for both operations and controlling its behavior through different control signals, the need for separate circuits is eliminated, thereby enabling vertical binning without increasing the fundamental size of the shift register.
Solution Approach 2:
The vertical shift register is designed to perform multiple functions: it can operate in normal reading mode to sequentially read charges from different rows, and in vertical binning mode to collectively read charges from multiple rows. This multi-functionality is achieved through a single shift register structure that responds to different control conditions, avoiding the need for additional dedicated circuits.
2Manufacturing precision
If photodetecting sections are fabricated on monocrystalline silicon wafers, then manufacturing precision is maintained, but the extent of photodetecting surfaces is limited
Solution Approach 1:
The patent uses polycrystalline silicon as a substitute material that replicates the essential functional properties of monocrystalline silicon for photodiode fabrication. While polycrystalline silicon can be formed on larger insulating substrates, it maintains the necessary electrical and optical characteristics to function as photodetecting sections, thereby enabling larger photodetecting surfaces without completely abandoning silicon-based fabrication.
3Adaptability or versatility
If the vertical shift register is increased in size to support vertical binning operation, then vertical binning operation is enabled, but integration degree decreases
Solution Approach 1:
The patent combines the functionality of normal row-by-row reading and vertical binning into a single integrated control mechanism within the existing vertical shift register. By using control signals to switch between operational modes rather than adding separate physical circuits, the integration degree is maintained while enabling vertical binning functionality.
Solution Approach 2:
The vertical shift register is designed as a universal structure that can perform both normal reading operations and vertical binning operations depending on control conditions. This multi-functionality eliminates the need for additional dedicated circuits for binning, thereby maintaining high integration度 while providing versatile operational capabilities.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A vertical shift register section 40a, 40b includes M logic circuits LO1 to LOM for outputting row selection control signals respectively to M row selection wiring lines LV,1 to LV,M and shift register circuits 43 disposed for every two row selection wiring lines LV. The M logic circuits LO1 to LOM, when a binning control signal Vbin1 or Vbin2 and an output signal of the shift register circuit 43 both have significant values, output a row selection control signal Vsel so as to close a readout switch SW1. The vertical shift register section 40a, 40b, by controlling the timing at which the binning control signals Vbin1 and Vbin2 take significant values, realizes a normal operation mode for successively selecting the two row selection wiring lines LV and a binning operation mode for simultaneously selecting the two row selection wiring lines LV. Accordingly, a vertical binning operation is realized by a small vertical shift register.