Imaging Sensor Transfer-Gate Overlap for Miniaturized Pixel Dark Current
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Solution Overview
Problem
In solid-state image sensors, miniaturization of pixels makes it difficult to secure space between the electrode of the charge transfer section and the high-concentration p-type impurity layer, leading to challenges in suppressing dark current attributed to interface states.
Innovation Solution
The imaging apparatus design includes a photoelectric converter with a first and second transfer transistor, where the control terminals of these transistors overlap a semiconductor region, forming a hole accumulation layer equivalent to a high-concentration p-type impurity layer, even in miniaturized pixels, by applying negative voltages to the control terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pixels are miniaturized to increase resolution, then the area of the photoelectric converter is reduced, but it becomes difficult to secure space between the electrode of the charge transfer section and the high-concentration p-type impurity layer, leading to increased dark current
Solution Approach 1:
The patent changes the electrical parameters (voltage levels and timing) of the transfer transistors to dynamically create a hole accumulation layer that functions equivalently to a high-concentration p-type impurity layer, allowing dark current suppression without requiring additional physical space in miniaturized pixels
Solution Approach 2:
The patent replaces the static physical structure (high-concentration p-type impurity layer) with a dynamic electrical control mechanism (transfer transistors applying negative voltage to accumulate holes), substituting a spatial solution with an electrical field-based solution that works effectively in miniaturized pixels
2Reliability
If a high-concentration p-type impurity layer is provided at the surface of the photoelectric converter to suppress dark current, then dark current is reduced, but it becomes difficult to miniaturize pixels due to the required space between the electrode and the impurity layer
Solution Approach 1:
The patent changes the operational parameters of the transfer transistors (gate voltage levels, pulse timing, and duration) to dynamically form a hole accumulation layer that provides dark current suppression functionality without requiring the physical space of a high-concentration p-type impurity layer
Solution Approach 2:
The patent transitions from a spatial solution (physical impurity layer requiring lateral space) to a temporal solution (time-dependent voltage application), using the time dimension to create and maintain the hole accumulation layer dynamically during specific operational phases, enabling dark current suppression in compact pixel structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses dark current in miniaturized pixels, ensuring high image quality and accurate distance measurement.
Implementation Method 1
the control terminals of these transistors overlap a semiconductor region, forming a hole accumulation layer equivalent to a high-concentration p-type impurity layer
Implementation Method 2
a photoelectric converter provided in the substrate
Data Source
AI summary
An imaging apparatus includes a substrate, a photoelectric converter provided in the substrate, a first transfer transistor connected to the photoelectric converter and including a first control terminal, and a second transfer transistor connected to the photoelectric converter and including a second control terminal. The photoelectric converter includes a first semiconductor region of a first conductivity type provided in the substrate. In a plan view of the substrate, each of the first control terminal and the second control terminal overlaps the first semiconductor region. The total of the overlapping area of the first control terminal and the first semiconductor region and the overlapping area of the second control terminal and the first semiconductor region is at least 20% of the area of the photoelectric converter.