In-Memory Computation Biasing Circuit for Linearity Compensation
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Solution Overview
Problem
In-memory computation systems face linearity and drift concerns due to memory element transconductance, which affect analog computation operations, necessitating compensation to improve accuracy and reliability.
Innovation Solution
The implementation of a biasing circuit with a series connection of transistors to apply a fixed reference voltage and a switching circuit controlled by coefficient data, combined with a column combining circuit to integrate analog signals, addresses the linearity and drift issues by maintaining a constant bit line voltage and performing accurate multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If in-memory computation is performed using memory element transconductance, then computation speed and energy efficiency are improved, but linearity and drift issues worsen affecting computation accuracy
Solution Approach 1:
The patent introduces a reference memory cell and reference bit line as intermediary elements to mediate between the computational memory cells and the readout circuitry. The reference cell experiences the same drift and linearity issues but provides a compensating reference signal that allows the system to cancel out these effects through differential measurement, thereby maintaining computation accuracy while preserving the speed benefits of in-memory computing
Solution Approach 2:
The patent implements feedback by using the reference bit line signal to compensate for drift and non-linearity in the computational bit lines. The readout circuitry continuously monitors the reference cell output and uses this information to correct measurements from the computational cells, creating a closed-loop system that maintains accuracy despite the inherent imperfections of memory element transconductance
2Loss of energy
If memory element transconductance is used for analog computation, then data transfer between memory and computing devices is eliminated, but drift and non-linearity adversely affect the computation operation
Solution Approach 1:
The reference memory cell serves as an intermediary that experiences the same environmental conditions and drift as the computational cells but provides a stable reference for differential measurement. This allows the system to eliminate data transfer between memory and computing devices while compensating for drift effects through the reference cell, thereby maintaining both energy efficiency and computation reliability
Solution Approach 2:
The patent changes the measurement parameter from absolute transconductance values to differential voltage differences between computational and reference bit lines. This parameter transformation allows the system to ignore common-mode drift effects while preserving the computational signal, enabling reliable analog computation without data transfer between devices
Data Source
AI summary
An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.