In-Memory Neural Memory Architecture Using Charge-Sharing Lanes

The patent replaces traditional von Neumann architecture with a memcomputing system where memory and processing are unified. The core innovation is using a crossbar array where memory cells store synaptic weights and input signals simultaneously, enabling parallel matrix multiplication through physical charge distribution rather than sequential computational steps. This substitution of computational mechanics with physical field interactions dramatically reduces processing time while maintaining ease of operation through high-level programming interfaces.

The patent employs multiple parameter optimization techniques: (1) Uses non-volatile memory cells that retain data without continuous power, eliminating standby power consumption; (2) Implements dynamic voltage and frequency scaling in the control logic to match operational intensity with power supply; (3) Optimizes the crossbar array dimensions and cell density to balance access speed with total device power consumption; (4) Uses charge-based computation that consumes energy only during actual compute operations rather than continuous clock cycles.

The patent divides the neural network computation into segmented operations: (1) Weight storage in memory cells separated from (2) input signal application through word lines, and (3) result readout through bit lines. The crossbar array itself is segmented into multiple banks that can be independently controlled. This segmentation allows each subsystem to be optimized independently and simplifies the control logic by breaking down complex operations into manageable stages, thereby reducing overall device complexity while maintaining high-speed parallel access.

The patent implements self-service mechanisms in the crossbar array where: (1) Memory cells automatically perform analog multiplication of weight and input values through charge coupling; (2) Bit lines automatically sum the results through capacitive integration; (3) The physical layout inherently provides synchronization through simultaneous signal propagation across the array. This eliminates the need for complex external control logic to coordinate parallel operations, as the hardware itself performs the coordination through its physical properties, thereby maintaining high processing efficiency while minimizing control complexity.