IMC Memory Arrays with Balance Cells and Capacitor Sensing
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Solution Overview
Problem
The limitations of existing in-memory computing (IMC) architectures include restricted input numbers due to memory array size, high energy consumption, reading errors from multiple input groups, non-uniform weight value distribution, and complex designs for handling large currents or resistances, which degrade neural network calculation efficiency.
Innovation Solution
An IMC memory device with a memory array comprising computing and balance computing memory cells, a loading capacitor, and a measurement circuit, where the resistance states are adjusted to optimize input voltages and currents, allowing for efficient summation and determination of operation results based on capacitor voltage and delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If inputs are separated into many input groups and sensed by several different SAs, then the number of inputs can exceed memory array size limits, but reading errors increase and energy consumption increases
Solution Approach 1:
The patent merges multiple input groups into a single sensing operation by using a unified sensing amplifier that can handle summed currents from all memory strings simultaneously. This allows the system to process more inputs than traditional separate SA approaches while maintaining reading accuracy and reducing energy consumption through consolidated sensing operations.
2Quantity of substance
If the number of inputs increases in sum-of-current architecture, then more data can be processed, but summation current becomes too large requiring complex SA design
Solution Approach 1:
The patent changes the sensing parameter from direct current measurement to voltage measurement across a capacitor. By integrating the summed current through a capacitor and measuring the resulting voltage, the system can handle large numbers of inputs without requiring complex high-current-capable sensing amplifiers, thus reducing SA design complexity while maintaining scalability.
3Productivity
If weight value distribution in memory strings is non-uniform, then memory utilization increases, but linearity of neural network calculation degrades
Solution Approach 1:
The patent implements a feedback mechanism where the system measures the actual current summation results and uses this information to dynamically adjust input values or weighting factors. This feedback loop compensates for non-uniform weight distributions in memory strings, maintaining calculation linearity while allowing flexible memory utilization patterns.
4Quantity of substance
If memory array size is increased to accommodate more inputs, then input capacity increases, but energy consumption and reading errors increase
Solution Approach 1:
The patent merges the sensing operations of all memory strings into a single capacitor charging operation. By summing currents from all strings simultaneously and measuring the combined effect on a single capacitor, the system achieves high input capacity while consuming less energy than traditional approaches that would require multiple separate sensing operations across expanded memory arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and accuracy of neural network calculations by optimizing current summation, reducing energy consumption, and improving linearity, while minimizing reading errors and design complexity.
Implementation Method 1
a loading capacitor coupled to the plurality of computing memory cells; the plurality of memory string currents from the plurality of memory strings charge the loading capacitor
Implementation Method 2
a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the plurality of computing memory cells generate a plurality of cell currents
Data Source
AI summary
An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.