In-Memory Computing Precision Control with Internal Clock Pulses
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Solution Overview
Problem
Existing in-memory computation (IMC) processing systems face inefficiencies when operating at less than the fixed bit precision supported by their hardware, leading to underutilization of processing resources.
Innovation Solution
Implementing a dynamic bit precision control mechanism that allows the IMC processing tile to switch between P-bit and Q-bit precision operations by using multiple P-bit multipliers and an internal clock generator to generate additional clock pulses, enabling efficient utilization of hardware resources for both lower and higher precision computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the IMC processing system uses fixed P-bit precision hardware, then the computation speed is high within one clock cycle, but the hardware resources are underutilized when higher Q-bit precision is required
Solution Approach 1:
The system dynamically adjusts bit precision by using an internal clock generator that produces multiple clock pulses within a single external clock cycle when Q-bit precision is required. This allows the fixed P-bit hardware to adaptively handle variable precision requirements without sacrificing computation speed or requiring multiple dedicated hardware units for different precision levels.
2Adaptability or versatility
If the IMC processing system uses fixed Q-bit precision hardware, then the hardware resources are fully utilized for higher precision operations, but the computation speed decreases when operating at lower P-bit precision
Solution Approach 1:
The system uses partial action by generating only the necessary number of internal clock pulses based on the required precision. When P-bit precision is needed, a single clock pulse is used; when Q-bit precision is needed, multiple pulses are generated. This avoids the excessive overhead of always operating with maximum precision while maintaining the capability to do so when required.
3Productivity
If multiple P-bit multipliers are used to achieve Q-bit precision, then the hardware complexity increases, but the computation can be completed within one clock cycle
Solution Approach 1:
The system uses periodic action by generating multiple sequential internal clock pulses within a single external clock cycle. Each pulse triggers a P-bit multiplication operation, and the results are accumulated to achieve Q-bit precision. This approach maintains computation speed by confining multiple operations within one external cycle while avoiding the need for multiple parallel multiplier circuits.
Data Source
Figure 1~2
Figure 3
Figure 4A~4B
AI summary
When a mode control signal indicates performance of an in-memory computation operation with a P-bit precision, a P-bit precision multiplier multiplies P-bits of feature data by P-bits of weight data to produce a computation output within one cycle of a clock signal. When the mode control signal indicates performance of the in-memory computation operation with a Q-bit precision, where Q=x*P, Q-bits of feature data are divided into P-bit blocks, the P-bit precision multiplier multiplies each P-bit block by P-bits of weight data in response to each pulse of an internal clock pulse, and the multiplication results are summed to produce the computation output within one cycle of a clock signal. A clock generator circuit generates x internal clock pulses for each cycle of the clock signal.