In-Memory Multiplier Precision Switching for Better MAC Utilization
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Solution Overview
Problem
Existing in-memory computation (IMC) processing tiles operate at a fixed bit precision, leading to inefficient utilization of hardware resources when lower precision is required, resulting in underutilization of processing capabilities.
Innovation Solution
Implementing a dynamic bit precision control mechanism that allows the IMC processing tiles to switch between P-bit and Q-bit precision operations by using multiple P-bit multipliers and an internal clock generator to generate additional clock pulses, enabling efficient utilization of hardware resources for both lower and higher precision computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed P-bit precision multipliers are used for all operations, then lower precision computations are efficient, but higher precision computations cannot be performed
Solution Approach 1:
The patent implements dynamic bit precision control that allows the IMC processing tile to switch between P-bit and Q-bit precision operations. The system uses multiple P-bit precision multipliers (first and second P-bit precision multipliers) that can be dynamically configured through a mode control signal to perform either P-bit operations or participate in Q-bit operations (where Q=x*P) by executing multiple cycles, thus providing adaptability without requiring fixed hardware for all precision levels
Solution Approach 2:
The patent segments higher precision Q-bit computations into multiple P-bit precision operations executed across multiple clock cycles. The first and second P-bit precision multipliers handle different portions of the computation, with results combined through addition circuits. This segmentation allows the system to achieve higher precision by breaking down complex Q-bit operations into manageable P-bit steps
2Measurement precision
If multiple P-bit precision multipliers are used to achieve Q-bit precision, then higher precision operations become possible, but computation time increases
Solution Approach 1:
The patent employs periodic clock signals to control the execution sequence of multiple P-bit precision operations. An internal clock generator produces a clock signal with a specific period that coordinates the timing of the first and second P-bit precision multipliers and the addition circuits. By using multiple clock cycles with periodic action, the system accumulates precision through successive operations while maintaining synchronized control
Solution Approach 2:
The patent performs preliminary configuration of the computation pipeline by setting up the mode control signal before execution. This preliminary action configures whether the system operates in P-bit mode (single cycle) or Q-bit mode (multiple cycles), allowing the computation path to be pre-established and optimized based on the required precision level before the actual computation begins
3Productivity
If dynamic precision control is implemented, then hardware resource utilization improves, but control mechanism complexity increases
Solution Approach 1:
The patent implements a universal control mechanism where the mode control signal serves multiple functions: it selects between P-bit and Q-bit precision modes, configures the operation of the first and second P-bit precision multipliers, and controls the clock generator. This single control signal provides multi-functionality that manages the entire dynamic precision system without requiring separate control circuits for each function, thereby improving hardware utilization while limiting control complexity
Data Source
AI summary
When a mode control signal indicates performance of an in-memory computation operation with a P-bit precision, a P-bit precision multiplier multiplies P-bits of feature data by P-bits of weight data to produce a computation output within one cycle of a clock signal. When the mode control signal indicates performance of the in-memory computation operation with a Q-bit precision, where Q=x*P, Q-bits of feature data are divided into P-bit blocks, the P-bit precision multiplier multiplies each P-bit block by P-bits of weight data in response to each pulse of an internal clock pulse, and the multiplication results are summed to produce the computation output within one cycle of a clock signal. A clock generator circuit generates x internal clock pulses for each cycle of the clock signal.