In-Memory Computing Processor with 2D Shift Accumulator

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Solution Overview

Problem

Existing in-memory computing (IMC) processors face inefficiencies in performing multiply and accumulate (MAC) operations due to the need for frequent data movement between memory and processing units, leading to high power consumption and limited performance.

Innovation Solution

The IMC processor incorporates SRAM IMC macros and a 2D shift accumulator to perform MAC operations directly in memory, with shared digital operators and a buffer system that prevents data loss during shift operations, allowing for efficient parallel processing and reduced data movement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If data is frequently moved between memory and processing units in conventional processors, then MAC operations can be performed, but power consumption increases and performance is limited

Engineering Contradiction:

Improvepower consumptionVSAvoidperformance

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The patent merges memory and processing units into an integrated in-memory computing architecture where MAC operations are performed directly within the memory array. Memory cells store both data and weight values, and computing operations are executed in-place without data movement between separate memory and processing components, thereby reducing power consumption while maintaining high performance

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a buffer structure as an intermediary between the memory array and external interfaces. This buffer temporarily holds data during MAC operations, enabling continuous computation without frequent data transfer to and from external memory, thus reducing power consumption while sustaining high computational throughput

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If general-purpose processors are used to execute CNN applications, then flexibility is maintained, but computation requires a considerable amount of time and resources

Engineering Contradiction:

Improvecomputation speedVSAvoidcomputational resources

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the computing task into distinct phases: data loading into the memory array, MAC operation execution within the memory array, and result output. This segmentation allows parallel execution of multiple MAC operations across different memory cells simultaneously, dramatically increasing computation speed while reducing overall energy consumption compared to sequential processing in general-purpose processors

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the mechanical data movement process inherent in conventional processors with an in-place computing mechanism. Instead of physically moving data between memory and processing units, the system performs computations directly where data is stored, eliminating the energy-intensive data transfer mechanism while accelerating computation

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If in-memory computing is implemented without a buffer system, then device complexity is reduced, but data loss may occur during shift operations

Engineering Contradiction:

Improvedata integrityVSAvoidbuffer system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a two-dimensional buffer structure with row buffers and column buffers that operate in perpendicular dimensions. This 2D arrangement allows the buffer to handle shift operations in both horizontal and vertical directions simultaneously, preventing data loss during MAC operations while maintaining a systematic and manageable complexity through the regular grid-like structure

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Productivity

If multiple IMC macros are used for parallel processing, then productivity increases, but device complexity increases

Engineering Contradiction:

Improveparallel processing capabilityVSAvoidnumber of IMC macros

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent designs the IMC macro as a universal building block that can be replicated and configured for different computational tasks. Each macro contains all necessary components (memory array, digital operators, buffer) to perform complete MAC operations independently. This universality allows multiple macros to work in parallel for different data sets or different stages of the same computation, increasing productivity while keeping each individual macro relatively simple and standardized

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240061649A1In-memory computing (IMC) processor and operating method of IMC processor

Publication Date: 2024.02.22 SAMSUNG ELECTRONICS CO LTD

AI summary

An in-memory computing (IMC) processor includes IMC macros, and includes a static random access memory (SRAM) IMC device including the plurality of IMC macros, and configured to perform a multiply and accumulate (MAC) operation between input data and first weight data of a first weight map applied to a first of IMC macros in a first direction in which an input feature map including the input data is written to the first IMC macro, and a two-dimensional (2D) shift accumulator configured to perform a shift operation on partial sums corresponding to respective MAC operation results of the IMC macros and accumulate a result of the shift operation.