Inter-Metal Dielectric Pattern Layout for Crack-Resistant Interconnects
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Solution Overview
Problem
The unbalanced stress between lower level metal interconnections and IMD layers in semiconductor devices leads to cracks, particularly in dense regions, affecting device performance due to the difference in stress types between tensile and compressive stresses.
Innovation Solution
A method involving the formation of a first IMD layer on a substrate, patterning it to create IMD patterns and trenches, depositing a metal layer within the trenches, and forming via conductors in a second IMD layer, ensuring IMD patterns are embedded within the metal layer without overlapping via conductors to balance stress evenly across the interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric material is used to fill gaps between metal lines, then interconnect capacitance is reduced and chip performance is improved, but unbalanced stress between metal interconnections and IMD layers creates cracks
Solution Approach 1:
The patent applies local quality by selectively removing low-k dielectric material from specific regions (via regions and regions adjacent to vias) while maintaining it in other areas. This creates local variations in dielectric properties to balance stress distribution - the removed regions reduce compressive stress that would otherwise cause cracking, while retained regions maintain low-k benefits for capacitance reduction.
Solution Approach 2:
The patent extracts low-k dielectric material from specific problematic regions through selective removal processes. By taking out the low-k material from via regions and adjacent areas, the patent eliminates the source of unbalanced compressive stress in those locations, preventing crack formation while preserving low-k benefits in other regions.
2Loss of energy
If low-k dielectric material is used, then interconnect capacitance is reduced, but compressive stress is generated in IMD layers creating cracks in dense via regions
Solution Approach 1:
The patent implements local quality by creating spatially varying dielectric structures - low-k material is removed from via regions and adjacent areas where compressive stress concentrates, while maintaining low-k material in other regions. This local differentiation addresses crack formation at via sites while preserving the energy-saving low-k benefits elsewhere.
Solution Approach 2:
The patent converts the harmful compressive stress effect of low-k dielectric into a beneficial stress management strategy by selectively removing low-k material from regions where compressive stress causes cracks. The stress that would be harmful in dense via regions is managed through strategic material removal, while the low-k material's energy-saving benefits are preserved in other areas.
Data Source
AI summary
A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.