Impedance Calibration Circuit Without ZQ RC Load in Memory Dies
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Solution Overview
Problem
As the operating speed of semiconductor memory devices increases, signal distortions due to impedance mismatch caused by process, voltage, and temperature variations become more pronounced, affecting the integrity of signals between the semiconductor memory device and the memory controller.
Innovation Solution
An impedance calibration circuit that generates reference voltage codes and control codes to adjust output impedance, independent of the ZQ node, thereby reducing RC load and maintaining operating speed even with multiple memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impedance calibration is performed using traditional ZQ node methods, then impedance matching is achieved, but operating speed decreases due to RC load
Solution Approach 1:
The patent extracts the impedance calibration function from the traditional ZQ node and implements it through a separate calibration circuit. The calibration circuit includes a calibration controller and calibration circuitry that can independently generate calibration signals without relying on the ZQ node, thereby eliminating the RC load bottleneck while maintaining impedance calibration capability
Solution Approach 2:
The patent segments the impedance calibration process into distinct functional blocks: a calibration controller that generates calibration commands, calibration circuitry that produces calibration signals, and separate pull-up/pull-down control circuits. This segmentation allows each component to operate independently at optimal speeds without being constrained by the ZQ node's RC characteristics
2Productivity
If multiple memory dies are commonly connected to share external resistor, then device integration is improved, but RC load increases affecting calibration speed
Solution Approach 1:
The patent extracts the impedance calibration function from the shared ZQ node infrastructure and implements it through dedicated calibration circuits in each memory die. Each die has its own calibration controller and calibration circuitry that can perform calibration independently, eliminating the cumulative RC load effect that would otherwise affect all shared dies
Solution Approach 2:
The patent segments the calibration function so that each memory die contains its own complete calibration subsystem (controller + circuitry). This segmentation allows parallel calibration operations across multiple dies without the RC load accumulation that would occur if all dies shared a common calibration node
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances signal integrity and maintains operating speed by eliminating the RC load associated with the ZQ node, ensuring efficient data transmission across multiple memory dies.
Implementation Method 1
generates a first reference voltage code when a voltage level of a selected reference voltage becomes the same as a first voltage of a first node coupled to the impedance pad by comparing the first voltage with the selected reference voltage
Data Source
AI summary
An impedance calibration circuit includes a calibration controller and a calibration circuit. The calibration controller generates a calibration enable signal based on an impedance calibration command. The calibration circuit, connected to an external resistor through an impedance pad, generates, in response to the calibration enable signal, a first reference voltage code when a voltage level of a selected reference voltage becomes the same as a first voltage of a first node, coupled to the impedance pad. The calibration circuit generates a pull-up control code based on the first reference voltage code, generates a second reference voltage code when the voltage level of the selected reference voltage becomes the same as a second voltage of a second node, and generates a pull-down control code based on the second reference voltage code.