Impedance Optimized Chip System Bond Wire Segmentation
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Solution Overview
Problem
Conventional single die solutions for high bandwidth switches face challenges with uncontrolled I/O port impedance, impedance mismatch, and increased wire sweep, leading to reduced packaging yield and higher costs.
Innovation Solution
The implementation of packaged IC circuits with multiple I/O ports having well-controlled characteristic impedance, achieved through novel segmentation and positioning of semiconductor chips and bond wires, optimizing bond wire lengths to match PCB transmission line impedance without additional impedance matching structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single integrated circuit chip is used to implement high bandwidth switches, then circuit density and bandwidth are improved, but I/O port impedance control deteriorates
Solution Approach 1:
The patent divides the single integrated circuit chip into multiple separate chips, each handling a subset of the high bandwidth signal lines. This segmentation allows each chip to have fewer I/O terminals, making impedance control feasible while maintaining overall system bandwidth through parallel operation of multiple chips.
2Productivity
If multiple high bandwidth I/O lines are implemented on a single IC die, then density and bandwidth are increased, but wire sweep increases
Solution Approach 1:
By segmenting the high bandwidth signal lines across multiple chips, each chip requires fewer bond wires connecting to the package. This reduction in the number of bond wires per chip directly reduces wire sweep, while the parallel configuration of multiple chips maintains the overall system bandwidth capability.
3Ease of manufacture
If conventional bond wire connections are used for package internal terminals to IC chip I/O terminals, then manufacturing simplicity is maintained, but impedance mismatch occurs
Solution Approach 1:
The patent applies local quality by reducing the number of bond wires per chip, which locally improves the characteristic impedance of each bond wire connection. This localized improvement in bond wire quality reduces impedance mismatch while maintaining the overall manufacturing simplicity of using bond wire technology.
Data Source
AI summary
A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.