Impedance Measurement Circuit Using Equivalent-Time Sampling

The patent employs periodic sampling of the power delivery network using a sampling clock signal that operates at a different frequency than the PDN excitation signal. By periodically sampling the voltage response at specific phases and accumulating multiple samples, the circuit achieves accurate impedance measurement without requiring the entire measurement process to run at reduced speed, thus resolving the contradiction between precision and testing time.

The patent performs preliminary phase alignment between the sampling clock signal and the PDN excitation signal before actual impedance measurement. By pre-synchronizing the sampling phases and using phase-locked loops to establish proper timing relationships, the system ensures that subsequent measurements can be conducted at full speed without compromising accuracy, thereby reducing overall testing time while maintaining precision.

The patent uses periodic sampling at optimized phases rather than continuous high-speed sampling. By strategically selecting sampling instants that correspond to specific phases of the PDN excitation cycle and accumulating multiple periodic samples, the system achieves both high productivity through faster overall profiling and maintained precision through proper phase-aligned sampling that captures the essential impedance characteristics.

The patent performs preliminary frequency synchronization and phase alignment between the sampling clock and PDN excitation signals. This preliminary action ensures that even when sampling at higher frequencies for faster profiling, the critical impedance information is captured at the correct phases, preventing precision deterioration while achieving improved productivity through faster accumulation of sufficient samples.