Impedance Control Circuit for Semiconductor Output Buffers
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining precise impedance control of their output buffers due to process irregularities and temperature changes, affecting their performance during read and write operations.
Innovation Solution
The implementation of an impedance-adjustable output buffer system, utilizing a calibration circuit and logic circuits to dynamically adjust the impedance of pull-up and pull-down units within the output buffers based on generated impedance codes, ensuring the output buffers operate at desired impedance levels during both read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the output buffer is designed with a fixed impedance, then the circuit structure is simple, but the impedance cannot be precisely controlled due to process irregularities and temperature changes
Solution Approach 1:
The patent applies dynamics by making the output buffer impedance adjustable rather than fixed. The output buffer includes a pull-up unit and pull-down unit whose impedance can be dynamically changed through calibration operations. The impedance adjusting circuit receives calibration data and adjusts the impedance of the output buffer to compensate for process irregularities and temperature changes, resolving the contradiction between simple structure and precise impedance control.
Solution Approach 2:
The patent applies parameter changes by varying the impedance parameters of the output buffer based on calibration data. The impedance adjusting circuit changes the impedance values of the pull-up and pull-down units according to stored calibration data that accounts for process irregularities and temperature variations. This allows precise impedance control while maintaining a relatively simple circuit structure through parameter adjustment rather than structural complexity.
2Reliability
If the impedance of the output buffer is adjusted during calibration, then precise impedance control is achieved, but the impedance may not be optimal for write operations where the output buffer functions as a termination resistor
Solution Approach 1:
The patent applies dynamics by enabling the output buffer impedance to be dynamically adjusted based on the operational mode. During read operations, the impedance is calibrated for optimal signal integrity. During write operations, the impedance adjusting circuit modifies the impedance values to optimize termination performance. This dynamic adaptation resolves the contradiction between maintaining precise impedance control for signal integrity and adapting to different operational requirements.
Solution Approach 2:
The patent applies parameter changes by modifying the impedance parameters of the output buffer according to the operational mode. The impedance adjusting circuit receives operational mode information and adjusts the pull-up and pull-down unit impedances accordingly. For read operations, calibration data optimizes signal integrity; for write operations, different parameter settings optimize termination function, resolving the adaptability contradiction.
3Reliability
If the output buffer impedance is optimized for read operations, then signal integrity is improved, but the performance during write operations may deteriorate
Solution Approach 1:
The patent applies dynamics by making the output buffer impedance可调 (adjustable) based on the operational mode. During read operations, the impedance is optimized for signal integrity through calibration. During write operations, the impedance adjusting circuit dynamically changes the impedance values to optimize write performance. This temporal differentiation resolves the contradiction between read and write operation performance optimization.
Solution Approach 2:
The patent applies parameter changes by modifying the impedance parameters of the output buffer according to the operational phase. Calibration data is used to adjust parameters for read operations to ensure signal integrity. For write operations, different parameter settings are applied to optimize productivity. This parameter adaptation across different operational phases resolves the performance contradiction.
Data Source
AI summary
Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.