Impedance Control Circuit for Replica Matching Error Cancellation
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Solution Overview
Problem
Conventional impedance control circuits for semiconductor devices suffer from significant adjust errors in pull-down replica circuits, which can be up to two bits of the count value, leading to inaccurate impedance control, especially when starting impedances are either lower or higher than the target values.
Innovation Solution
The implementation of a control circuit that adjusts the impedances of first and second replica circuits in a stepwise manner, with detection signals terminating the impedance change when the impedance reaches or crosses a reference value at least twice, ensuring accurate impedance matching by canceling adjust errors between the two circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If impedance control is performed using a counter circuit that adjusts replica circuits stepwise, then the impedance control operation is simple and systematic, but the obtained impedances are discrete values resulting in adjust errors up to two bits of the count value
Solution Approach 1:
The patent applies preliminary action by first adjusting the pull-up replica circuit impedance to match the external resistor impedance before adjusting the pull-down replica circuit. This sequential approach ensures that the pull-down circuit adjustment starts from a known reference point, reducing cumulative errors. The control circuit finishes updating the pull-up counter before starting the pull-down counter update, implementing a systematic preliminary adjustment sequence.
Solution Approach 2:
The patent implements feedback by having the control circuit continuously monitor the impedance of both pull-up and pull-down replica circuits during the impedance control operation. The control circuit detects when each replica circuit impedance reaches its target value and uses this feedback information to determine when to finish updating the respective counter values, enabling precise termination of the adjustment process.
2Stability of the object's composition
If the impedance of the pull-down replica circuit is adjusted based on the impedance of the pull-up replica circuit, then the impedance control follows a systematic sequence, but the adjust error of the pull-down replica circuit accumulates to up to two bits of the count value
Solution Approach 1:
The patent applies preliminary action by completing the pull-up replica circuit impedance adjustment entirely before initiating the pull-down replica circuit adjustment. The control circuit finishes updating the pull-up counter value before starting to update the pull-down counter value, ensuring that the pull-down adjustment is based on a stable, finalized pull-up reference rather than a changing value, thereby preventing error accumulation.
Solution Approach 2:
The patent segments the impedance control operation into two distinct phases: first adjusting the pull-up replica circuit independently to match the external resistor, then adjusting the pull-down replica circuit independently to match the pull-up replica circuit. This segmentation isolates the adjustment processes, preventing相互 interference and error propagation between the two circuits.
3Speed
If the counter circuit updates the count value to reduce impedance when the impedance is higher than the target impedance, then the impedance control moves toward the target value, but the discrete nature of count value updates causes the impedance to exceed the target impedance by one bit of the count value
Solution Approach 1:
The patent applies partial action by having the control circuit terminate the counter update process precisely when the impedance reaches or crosses the target value, rather than allowing a full count step to complete. The control circuit detects the crossing point and finishes updating the counter value at that moment, effectively using a partial count step to achieve better accuracy than full discrete steps would allow.
Data Source
AI summary
To include two counter circuits that change impedances of two replica circuits, respectively, and an impedance adjustment control circuit that controls the counter circuits to update count values of the counter circuits. The impedance adjustment control circuit controls one of the counter circuits to finish updating the count value of the counter circuit in response to a change of the impedance of the corresponding replica circuit from a state of being lower than an impedance of an external resistor to a state of being higher than the impedance of the external resistor, and controls the other counter circuit to finish updating the count value of the other counter circuit in response to a change of the impedance of the other replica circuit from a state of being higher than the impedance of the former replica circuit to a state of being lower than the impedance of the former replica circuit. With this configuration, the adjust errors generated in the replica circuits are canceled.