Impedance Gain Circuit for High-Speed DAC Linearity

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Solution Overview

Problem

High-speed digital to analog converters (DACs) face challenges in maintaining high linearity due to non-ideal current sources, which result in decreased output current as output voltage increases, affecting video signal quality.

Innovation Solution

The implementation of a current source with an impedance gain circuit, comprising PMOS transistors and a pull-up electric potential module, increases the output impedance of the current source, improving linearity by adding gain stages to the current steering structure of conventional DACs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional current source is used in a high-speed DAC, then the circuit structure is simple, but the output impedance is insufficient causing current to decrease as output voltage increases, degrading linearity

Engineering Contradiction:
ImproveDAC linearityVSAvoidcircuit structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces an impedance gain circuit as an intermediary component between the current output circuit and the load. This circuit includes a third PMOS transistor, a fourth PMOS transistor, and a pull-up electric potential module that work together to amplify the output impedance without requiring complete redesign of the current source architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent adds a new dimensional layer to the current source by introducing the impedance gain circuit stage. This additional circuit layer transforms the output characteristics by providing impedance multiplication through the cascaded transistor configuration, effectively separating the current generation function from the impedance transformation function.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the output impedance of the current source is increased to approach ideal behavior, then DAC linearity improves, but the circuit complexity increases due to additional components

Engineering Contradiction:
Improvecurrent source performanceVSAvoidnumber of transistors
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the output impedance parameter of the current source by introducing the impedance gain circuit. The third and fourth PMOS transistors are configured to provide impedance multiplication, transforming the original output impedance into a significantly higher value that approaches ideal current source behavior.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the current source functionality into two distinct parts: the current output circuit (first and second PMOS transistors) responsible for current generation, and the impedance gain circuit (third and fourth PMOS transistors plus pull-up module) responsible for impedance transformation. This segmentation allows each part to be optimized independently.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10312934B2Current source and digital to analog converter
Publication Date: 2019.06.04 SEMICON MFG INT (BEIJING) CORP
  • US10312934B2 patent drawing
  • US10312934B2 patent drawing
  • US10312934B2 patent drawing

AI summary

The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. The current output circuit includes a first PMOS transistor and a second PMOS transistor. The impedance gain circuit includes a first end, a second end, a third end which is connected to a supply voltage, and a fourth end which is connected to the ground. A source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage. A gate electrode of the second PMOS transistor is connected to the second end of the impedance gain circuit, and a drain electrode of the second PMOS transistor serves as an output end of the current source.