Impedance Match Uniformity Circuit for Plasma Etch Rate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In plasma processing of wafers, variations in etching rates across the surface lead to increased difficulties in fabricating uniform additional layers due to uneven surface topography, making precise impedance matching challenging.
Innovation Solution
A uniformity control circuit is integrated at the output of an impedance match, utilizing a combination of RF straps and capacitors to modify the capacitance and achieve uniformity in the processing rate across the substrate's surface, allowing for a uniform topography and consistent layer fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a plasma process is applied to etch features on a wafer, then material removal is achieved, but non-uniform etching rates across the wafer surface occur
Solution Approach 1:
The patent applies local quality by introducing a uniformity control circuit that provides different impedance matching conditions to different regions of the wafer. The circuit includes multiple RF straps (first, second, third RF straps) that can be independently adjusted to compensate for local variations in etching rates across the wafer surface, ensuring uniform processing despite spatial variations in plasma distribution.
Solution Approach 2:
The patent employs parameter changes by modifying the electrical impedance parameters of the RF matching circuit. The uniformity control circuit adjusts capacitance and inductance values in different circuit branches to optimize power distribution across the wafer surface. This allows dynamic adjustment of RF power parameters to achieve uniform etching rates while maintaining high productivity.
2Productivity
If the etching rate varies across the wafer surface, then material removal occurs at different rates, but this creates increased surface topography variations
Solution Approach 1:
The uniformity control circuit implements local quality by providing region-specific impedance adjustment through multiple RF straps. Each RF strap can be independently tuned to address local topography issues in specific wafer regions, ensuring that material removal rates are equalized across the entire surface while maintaining the desired productivity level.
Solution Approach 2:
The patent incorporates feedback mechanisms where the uniformity control circuit monitors etching uniformity and adjusts RF power distribution accordingly. By measuring variations in surface topography and etching rates, the system dynamically modifies impedance parameters to compensate for deviations, thereby maintaining uniform surface morphology while achieving high material removal rates.
3Manufacturing precision
If a uniformity control circuit is added to the impedance match, then etching uniformity is improved, but device complexity increases
Solution Approach 1:
The uniformity control circuit is segmented into multiple independent RF strap circuits (first, second, third RF straps), each handling a specific region of the wafer. This segmentation allows for localized adjustment without requiring complete redesign of the entire matching circuit, thereby improving etching uniformity while keeping the complexity of each individual circuit segment manageable and modular.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures a uniform etch rate across the substrate's surface, facilitating the fabrication of uniform additional layers and improving the overall precision and efficiency of the plasma processing.
Implementation Method 1
The uniformity control circuit also includes a third RF strap coupled to the capacitor and to the first RF strap. The first RF strap is coupled between an output of an impedance matching circuit and an RF transmission line that is coupled to a plasma chamber.
Data Source
AI summary
An impedance match housing is described. The impedance match housing includes an impedance matching circuit having an input that is coupled to a radio frequency (RF) generator. The impedance matching circuit has an output that is coupled to a first RF strap. The impedance match housing includes a uniformity control circuit coupled in parallel to a portion of the first RF strap to modify uniformity in a processing rate of a substrate when the substrate is processed within a plasma chamber.