Impedance Matching Device Switching Cycle Optimization

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Solution Overview

Problem

High-frequency impedance matching devices generate excessive heat due to frequent on-off operations of semiconductor switches when dealing with loads like plasma, leading to inefficiencies and potential damage.

Innovation Solution

The impedance matching device employs a dual-capacitance element group configuration, where a first group with higher capacitance performs initial rough adjustments and a second group with lower capacitance performs precise adjustments, using distinct update cycles to minimize switching losses and heat generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If continuous updating of semiconductor switch states is performed to track load impedance variations, then impedance matching accuracy is improved, but heat generation due to switching loss increases

Engineering Contradiction:
Improveimpedance matching accuracyVSAvoidswitching loss
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The capacitor group is segmented into multiple subsets, each with different capacitance values. The control unit selectively updates switches in different subsets at different rates, performing frequent updates on a first subset for coarse adjustment and less frequent updates on a second subset for fine adjustment, thereby reducing overall switching loss while maintaining matching accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control unit implements periodic updating of semiconductor switch states with varying periods. During initial impedance matching, updates are performed at a first period; after matching is achieved (when reflected power is below threshold), updates are performed at a second, longer period, reducing switching frequency and heat generation while maintaining matching quality

Inventive Principle:
Principle #19Periodic action

2Productivity

If frequent switching control is applied to track plasma load impedance changes, then power supply efficiency is improved, but heat generation in semiconductor switches increases

Engineering Contradiction:
Improvepower supply efficiencyVSAvoidheat generation
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The control unit dynamically adjusts the updating period of semiconductor switch states based on the matching state. When impedance matching is achieved (reflected power below threshold), the updating period is extended from a first period to a second, longer period, reducing switching frequency and heat generation while maintaining power supply efficiency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control unit performs full switching control only when necessary (during initial matching or when matching deteriorates). Once matching is achieved, it reduces to partial updating of switch states at longer intervals, maintaining sufficient power supply efficiency while reducing heat generation from excessive switching

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11218129B2Impedance matching device and impedance matching method
Publication Date: 2022.01.04 DAIHEN CORP
  • US11218129B2 patent drawing
  • US11218129B2 patent drawing
  • US11218129B2 patent drawing

AI summary

An impedance matching device 1 includes multiple capacitance elements and a control unit that controls on or off of semiconductor switches. The capacitance elements and respectively include a first capacitance element group and a second capacitance element group. The control unit updates the state of the first semiconductor switch included in the first capacitance element group with a first cycle until a predetermined time period elapses during which the state of the first semiconductor switch included in the first capacitance element group is maintained while the control unit updates the states of the semiconductor switch and respectively included in the first capacitance element group and the second capacitance element group with a second cycle longer than the first cycle after the predetermined time period elapses during which the state of the first semiconductor switch included in the first capacitance element group is maintained.