Impedance Mismatch Detection Circuit for PVT-Tolerant I/O Control
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Solution Overview
Problem
In high-speed, high-bandwidth electronic circuits, such as those used in memory interfacing, it is challenging to accurately control impedance mismatch between pull-up and pull-down devices over variations in PVT conditions without increasing the number of PVT bits, which can lead to increased design complexity and layout area penalties.
Innovation Solution
A comparison circuit is implemented that detects impedance mismatch by generating signals indicative of the difference between reference pull-up and pull-down currents, scaled by a prescribed amount, and uses a comparator to generate a signal indicative of impedance mismatch threshold, thereby reducing design complexity and layout area without increasing the number of bits in the PVT compensation circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of PVT bits in the compensation circuit is increased to improve impedance mismatch detection accuracy, then the impedance control precision is improved, but the device complexity and layout area increase
Solution Approach 1:
The patent introduces an intermediary comparison circuit that includes a comparator and signal generators. This intermediary circuit processes the impedance mismatch detection by comparing signals representing pull-up and pull-down impedances, and generates control signals based on the comparison result. This mediator approach allows accurate impedance control without directly increasing the number of PVT bits in the main compensation circuit.
Solution Approach 2:
The patent creates simplified copies of the impedance characteristics through signal generators that produce signals representative of the pull-up and pull-down impedances. Instead of directly monitoring and controlling all impedance variations with multiple PVT bits, the system uses copied signal representations that can be compared and used to generate control signals, reducing the complexity of the compensation circuit.
2Measurement precision
If the number of PVT bits is increased to reduce impedance mismatch, then the measurement precision of impedance detection is improved, but the layout area and design complexity increase
Solution Approach 1:
The comparison circuit acts as an intermediary that performs the precise measurement function. The comparator compares signals representing the impedances and generates control signals based on the comparison, achieving precise impedance mismatch detection without requiring additional PVT bits that would occupy more layout area.
Solution Approach 2:
The patent replaces the mechanical approach of using more PVT bits (which would physically occupy more area) with an electronic signal processing approach. The comparison circuit uses electrical signal comparison and digital logic to achieve precise measurement, substituting the physical expansion approach with an electronic processing solution that maintains compact layout.
3Manufacturing precision
If the PVT compensation circuit uses more control bits to accurately control pull-up and pull-down impedances, then the impedance mismatch control is improved, but the pad capacitance and design complexity increase
Solution Approach 1:
The patent extracts the precise impedance control function into a separate comparison circuit module. By taking out the detection and control logic into this dedicated circuit with comparator and signal generators, the main PVT compensation circuit can use fewer bits, thereby reducing the associated pad capacitance while maintaining accurate impedance mismatch control through the extracted comparison functionality.
Data Source
AI summary
A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.