Programmable Impedance Element Pulse Delay Verification
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Solution Overview
Problem
Conventional non-volatile memory technologies, such as flash memory, face limitations in power consumption and operation speed, while resistive RAM (ReRAM) and conductive bridging RAM (CBRAM) offer lower power and higher speeds but struggle with program and erase operation efficiency due to reverse effects and unipolar phenomena, leading to increased cell resistance and operational failures.
Innovation Solution
Implementing a method that includes generating program and erase pulses followed by time delays to allow for the partial dissipation of effects caused by these operations, with verify operations conducted after the delays to ensure successful programming or erasing of programmable impedance elements, utilizing a command decoder, program/erase operation controller, delay controller, and verify operation controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If program and erase operations are performed immediately without delay, then operation speed is improved, but program and erase reliability deteriorate due to reverse effects and unipolar phenomena
Solution Approach 1:
The patent applies preliminary action by inserting a delay period between the program/erase pulse and the verify operation. This delay allows temporary effects such as reverse program/erase effects and unipolar phenomena to dissipate before verification occurs, ensuring accurate detection of the actual program/erase state without interference from transient effects.
Solution Approach 2:
The patent implements beforehand cushioning by introducing a time delay that acts as a buffer between the program/erase operation and the verify operation. This cushioning period allows harmful temporary effects to subside, preventing them from causing verification errors and improving overall operation reliability.
2Loss of time
If verify operation is performed immediately after program pulse, then time efficiency is improved, but measurement precision deteriorates due to temporary effects from program operation
Solution Approach 1:
The patent applies preliminary action by performing the delay operation before the verify operation. This preliminary delay allows temporary program effects to dissipate, ensuring that when verification occurs, the measurement is not contaminated by transient effects, thus improving verify precision.
Solution Approach 2:
The patent implements skipping by rapidly performing the delay period without unnecessary intermediate operations. The delay is implemented efficiently to minimize time loss while still allowing sufficient time for temporary effects to dissipate, balancing speed and precision requirements.
3Productivity
If erase operation is performed without additional delay, then productivity is improved, but manufacturing precision deteriorates due to unipolar phenomena affecting resistance window
Solution Approach 1:
The patent applies preliminary action by inserting a delay period after the erase pulse before verification. This delay allows unipolar phenomena and other temporary effects to dissipate, ensuring that the resistance window measurement during verification accurately reflects the true erase state, thereby improving manufacturing precision.
Solution Approach 2:
The patent implements parameter changes by adjusting the timing parameter (delay duration) to optimize the balance between productivity and precision. The delay period is carefully controlled to be sufficient for effect dissipation but not excessively long, maintaining efficient erase operation while improving resistance window measurement accuracy.
Data Source
AI summary
Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of programming/erasing the programmable impedance element can include: (i) receiving a program/erase command to be executed on the programmable impedance element; (ii) generating, in response to the program/erase command, a program/erase pulse for performing a program/erase operation on the programmable impedance element; (iii) generating a time delay from the program/erase pulse, where the time delay includes additional delay to allow for at least partial dissipation of one or more effects caused by the program/erase operation; and (iv) performing, after the time delay has elapsed, a verify operation to determine if the program/erase operation has successfully programmed/erased the programmable impedance element.