Imperative Language Circuit Translator
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Solution Overview
Problem
There is a need for a method and apparatus to translate imperative programming language descriptions of circuits into hardware descriptions, allowing designers to map software objects to appropriate hardware components for instantiation in hardware descriptions, as existing tools primarily process hardware description languages (HDLs) and lack direct support for imperative programming languages like C, C++, and MATLAB.
Innovation Solution
A system comprising a programming environment, a translator, and an implementation system that identifies state objects in imperative programming language descriptions and maps them to hardware objects based on criteria, generating a hardware description that can be implemented into programmable logic devices or integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard implementation tools process HDL descriptions into hardware, then hardware implementation is achieved, but direct support for imperative programming languages is lacking
Solution Approach 1:
The patent introduces a translator as an intermediary component that converts imperative programming language descriptions into HDL descriptions. This translator acts as a mediator between the programming environment and the implementation system, allowing designers to use familiar programming languages while still leveraging existing HDL-based hardware implementation tools. The translator includes state machine generation logic that automatically converts software constructs into hardware-equivalent state machines, thereby extending language support without requiring complete redesign of the implementation toolchain.
2Adaptability or versatility
If a translator maps software objects to hardware components, then bridging between software and hardware design flows is achieved, but device complexity increases
Solution Approach 1:
The translator is segmented into distinct functional modules: state object identification, state machine generation, and HDL code generation. Each module handles a specific aspect of the translation process, making the overall system more manageable and maintainable. The state object identification module analyzes programming language constructs, the state machine generation module creates hardware-equivalent state representations, and the HDL code generation module outputs synthesizable hardware descriptions. This segmentation reduces translator complexity by breaking down the monolithic translation task into manageable components.
Solution Approach 2:
The translator is designed with universal capabilities to handle multiple imperative programming languages (C, C++, MATLAB) through a common translation framework. The state machine generation logic is language-agnostic, recognizing stateful constructs across different programming paradigms and converting them into unified hardware representations. This multi-functionality allows the same translator infrastructure to serve diverse programming languages without requiring language-specific implementation paths, thereby reducing overall system complexity despite the broad adaptability.
3Manufacturing precision
If state objects are mapped to hardware objects based on criteria, then accurate hardware instantiation is achieved, but translation complexity increases
Solution Approach 1:
The translator performs preliminary analysis of state objects during the translation process, identifying their characteristics and mapping them to appropriate hardware objects before generating the final HDL code. The system pre-processes programming language constructs to determine state object properties (such as data type, access patterns, and lifecycle), then matches these properties against criteria for hardware object instantiation. This preliminary action ensures accurate mapping by making translation decisions based on analyzed characteristics rather than generic rules, thereby improving manufacturing precision while managing translation complexity through structured analysis.
Data Source
AI summary
Method and apparatus for translating an imperative programming language description of a circuit into a hardware description is described. In one example, a state object in a function of the imperative programming language description is identified. Use of the state object in the function is compared against criteria associated with each of a plurality of hardware objects. The state object is mapped to a hardware object of the plurality of hardware objects such that the use of the state object in the function satisfies the criteria of the hardware object. At least one instance of the hardware object is generated in the hardware description.