Implanted Isolation Structure for Mixed-Transistor Integration
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Solution Overview
Problem
The integration of high-electron-mobility transistors with other types of transistors, such as field-effect or heterojunction bipolar transistors, on a semiconductor substrate is complex due to the need for electrical isolation, which is challenging with existing CMOS processing methods and engineered substrates.
Innovation Solution
A semiconductor substrate with first and second device regions, where a polycrystalline layer is formed beneath the first device region and a layer stack of III-V compound semiconductor material is used in the second device region to create transistors, with shallow trench isolation regions and epitaxial growth processes to promote lattice matching and reduce defectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafer bonding or engineered substrates are used to integrate high-electron-mobility transistors with other transistors, then device integration is achieved, but process complexity increases significantly
Solution Approach 1:
A buried isolation layer is introduced as an intermediary structure between different transistor regions on the same substrate. This isolation layer acts as a mediator that enables electrical isolation between high-electron-mobility transistors and other transistor types, allowing integration without requiring complex wafer bonding or engineered substrates.
Solution Approach 2:
The substrate is segmented into different device regions with distinct transistor types, separated by the buried isolation layer. This segmentation allows each region to be optimized for its specific transistor type while maintaining overall integration on a common substrate, reducing the need for complex hybrid substrate engineering.
2Adaptability or versatility
If different transistor types are integrated on the same substrate, then device functionality is enhanced, but electrical isolation becomes challenging
Solution Approach 1:
The buried isolation layer serves as an electrical intermediary that blocks current flow between different transistor regions. By positioning this isolation layer at a depth that intersects with the substrate regions underlying different transistor types, reliable electrical isolation is achieved while maintaining the functionality of both high-electron-mobility and other transistor types on the same chip.
3Speed
If III-V compound semiconductor materials are used for high-electron-mobility transistors, then carrier mobility is improved, but crystalline defectivity increases
Solution Approach 1:
The buried isolation layer is formed preliminarily before growing the III-V compound semiconductor layers. This preliminary action creates a isolation structure that prevents defect propagation from the substrate into the III-V layers, allowing the high carrier mobility benefits of III-V materials to be realized while minimizing crystalline defectivity through the isolation barrier.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the effective integration of high-electron-mobility transistors with other types of transistors by providing enhanced electrical isolation and reducing crystalline defectivity, improving the complexity and performance of transistor integration.
Implementation Method 1
shallow trench isolation regions and epitaxial growth processes to promote lattice matching and reduce defectivity
Implementation Method 2
epitaxial growth processes to promote lattice matching and reduce defectivity
Data Source
AI summary
Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.