Implanted STI Regions for Leakage-Resistant GAA FET Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in preventing current leakage in nanostructure FET devices due to damage of shallow trench isolation (STI) regions during fabrication processes, leading to degradation of AC performance and merge defects.
Innovation Solution
Implementing dopant implantation processes into the STI regions at various stages of the fabrication process to modify dielectric properties and prevent loss of STI regions, thereby preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used without dopant implantation, then the fabrication process is simpler, but STI regions are damaged during etch and cleaning processes causing current leakage
Solution Approach 1:
Dopant implantation is performed in advance at specific fabrication stages (after isolation structures, dummy oxide formation, and gate spacer creation) to modify the dielectric properties of STI regions before they are exposed to damaging etch and cleaning processes. This preliminary modification prevents STI region loss and subsequent current leakage.
Solution Approach 2:
The dielectric properties of STI regions are modified by changing the dopant concentration through implantation processes. By adjusting implantation dosage and energy, the STI regions gain enhanced resistance to damage during subsequent fabrication steps, thereby improving reliability without fundamentally changing the fabrication process flow.
2Reliability
If dopant implantation is performed at multiple stages, then STI region protection is improved, but the number of fabrication steps increases
Solution Approach 1:
Dopant implantation is strategically performed at three key preliminary stages (after isolation structures, dummy oxide formation, and gate spacer creation) to provide progressive protection to STI regions. This timing ensures that STI regions are fortified before each potentially damaging process, preventing current leakage while integrating seamlessly into the existing fabrication flow.
Solution Approach 2:
The implantation parameters (dosage, energy, timing) are optimized to provide effective STI protection with minimal impact on overall productivity. By performing implantation at specific stages rather than continuously, the process achieves reliable current leakage prevention while maintaining reasonable fabrication throughput.
3Reliability
If dopant implantation is used to protect STI regions, then current leakage is reduced, but the fabrication process becomes more complex
Solution Approach 1:
The dielectric properties of STI regions are modified through controlled dopant implantation, changing the electrical and physical parameters of the STI material. This parameter modification enhances AC performance by preventing current leakage paths, while the implantation process itself is integrated into existing fabrication stages to minimize overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implantation process effectively prevents STI region loss and current leakage without affecting the sidewalls of other layers, enhancing the reliability and performance of GAA FET devices.
Implementation Method 1
implanting dopants into at least an upper portion of the isolation structure
Data Source
AI summary
A method for fabricating semiconductor devices includes forming a stack structure protruding from a substrate and including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked on top of one another. The method includes forming an isolation structure overlaying the substrate and a lower portion of the stack structure. The method includes implanting dopants into at least an upper portion of the isolation structure.