Implicit Addressing Electronic Units Counter Comparison
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Solution Overview
Problem
Existing methods for addressing electronic units on bus wires rely on explicit addressing, which requires address pins and data pins, and often uses multiplexing, leading to inefficiencies and overhead in data transmission.
Innovation Solution
A method for implicit addressing using counter units and comparison units within electronic units, allowing data transmission without explicit addresses by setting and comparing counter values, enabling fast read and write access without address data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If explicit addressing is used with address pins and data pins, then data transmission can be performed, but device complexity increases and data overhead increases
Solution Approach 1:
The patent extracts the addressing function from the traditional explicit addressing mechanism. Instead of using separate address pins and data pins, the system uses a time-division multiplexed bus where units are identified by their temporal position in a sequence, eliminating the need for dedicated address lines while maintaining unique identification capability.
Solution Approach 2:
The data bus is made universal by serving dual purposes: it carries both data and implicit addressing information. The same physical bus that transmits data also determines which unit should receive or send the data based on the temporal sequence and counter comparison, eliminating the need for separate address transmission infrastructure.
2Speed
If explicit addressing with multiplexing is used, then data transmission is enabled, but data transmission speed decreases due to overhead
Solution Approach 1:
The system performs preliminary action by pre-configuring each unit with a unique identifier and initializing counter registers to the same start value before data transmission begins. This setup allows the units to automatically determine their turn to transmit or receive data through counter comparison without requiring explicit address preparation during the data transmission process itself.
Solution Approach 2:
The patent implements a skipping mechanism where units that are not currently supposed to transmit or receive data skip their turn by having their counter comparison fail. The active unit is determined by which unit's counter matches its identifier first in the sequence, allowing rapid data transmission without stopping for address validation or preparation.
3Productivity
If implicit addressing with counter units is used, then data transmission speed increases, but device complexity changes requiring counter and comparison units
Solution Approach 1:
The patent merges the addressing function with the data transmission function by combining counter units and comparison units into the existing data bus architecture. Instead of adding separate addressing hardware, the system integrates the counter and comparison logic into the data transmission protocol, where the same bus lines carry both data and control information for unit identification.
Solution Approach 2:
Each unit serves itself by using its own unique identifier and locally maintained counter register to determine when it should transmit or receive data. The comparison unit within each unit automatically compares its counter value with its identifier without requiring external addressing signals, making the system self-addressing and eliminating the need for complex external address generation hardware.
Data Source
AI summary
A method for implicit addressing includes providing within a first unit and a second unit respectively a counter unit, a comparison unit and a storing unit for the storage of an identifier, allocating a first identifier to the first unit, allocating a second identifier to the second unit setting the same counter value in the counter units of both units, after setting the counter values comparing the counter value in the first unit to the first identifier and comparing the counter value in the second unit to the second identifier, based on equality of the comparison in the first unit sending of first data from the first unit or-assigning of first data to the first unit, based on inequality of the comparison in the second unit no sending or assigning of data to the second unit, and counting up or down the counter value in both units.