Implicit Global Pointer Relative Addressing for Memory Access
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Solution Overview
Problem
Existing instruction set architectures (ISAs) for memory access are inefficient due to the need for multiple instructions to access global data, particularly when using displacement addressing or constant pool addressing, and limited address ranges in PC-relative and GP-relative addressing modes.
Innovation Solution
The introduction of an ISA with instructions that implicitly identify the Global Pointer (GP) register as an operand, allowing for extended offset ranges and immediate values, thereby reducing the number of instructions required for global memory access and increasing code density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If displacement addressing or constant pool addressing is used to access global data, then memory access can be performed, but multiple instructions are required which reduces code density and efficiency
Solution Approach 1:
The patent combines the base register value and offset into a single unified address generation operation. By implicitly using the GP register as the base and allowing the offset field in the instruction to directly combine with GP to form the complete address, the patent merges what would traditionally require separate instructions (loading base register and performing address calculation) into a single memory access instruction.
2Device complexity
If PC-relative or GP-relative addressing modes are used, then code density improves, but the address range is limited
Solution Approach 1:
The patent extends the address range by effectively adding another dimension to the offset field. By allowing the offset to be combined with the GP register in a way that utilizes the full register width (e.g., combining a 16-bit offset with the upper bits of GP to form a 32-bit address), the patent expands the accessible address space from what would be limited by a simple relative offset to a much larger range while maintaining the single-instruction format.
3Adaptability or versatility
If explicit base register identification is included in instructions, then flexibility is maintained, but instruction bits are consumed reducing offset size
Solution Approach 1:
The patent extracts the base register identification from the instruction format by implicitly designating the GP register as the base. This removes the need for explicit base register fields in instructions that use GP-relative addressing, freeing up instruction bits that can then be allocated to extend the offset field size and thereby increase the accessible address range.
Data Source
AI summary
Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.