Implicit Unknown Value Generation in HDL Enumerated Data Constructs
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Solution Overview
Problem
In Hardware Descriptive Language (HDL) designs, ensuring all variables and structures are properly initialized without explicitly creating additional states for unknown values is laborious and can lead to extraneous hardware logic being fabricated, as existing methods require manual modification and maintenance of thousands of code lines to prevent wasteful logic generation.
Innovation Solution
A method and system that automatically generates an implicit unknown value in user-defined enumerated type data constructs during HDL design compilation and simulation, maintaining compatibility with the VHDL Language Reference Manual by inserting an additional literal value and modifying case statements and attributes to account for the unknown state, thereby ensuring proper initialization without modifying user code extensively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional uninitialized state is explicitly created in HDL design, then initialization control is improved, but code complexity and modification effort increase significantly
Solution Approach 1:
The system automatically generates and manages the uninitialized state representation without requiring manual user intervention. The compiler/simulation tool autonomously handles the creation of the additional state, modification of case statements, and updates to predefined attributes, eliminating the laborious manual task of checking and modifying thousands of variables and structures
Solution Approach 2:
The uninitialized state is automatically created and integrated into the HDL design during the compilation or simulation setup phase, before the actual design verification begins. This preliminary automatic setup ensures that all variables and structures are properly tracked for initialization status without requiring subsequent manual intervention
2Measurement precision
If unknown values are explicitly defined in HDL code, then simulation accuracy is improved, but extraneous hardware logic is fabricated during synthesis
Solution Approach 1:
The system introduces an implicit uninitialized state that acts as an intermediary representation during simulation only. This state is automatically managed by the compilation/simulation system and is not carried forward to synthesis, thereby maintaining simulation accuracy while preventing the fabrication of extraneous hardware logic
Solution Approach 2:
The system changes the state of variables and structures to an automatically generated uninitialized state during simulation, allowing accurate tracking of initialization status. During synthesis, this state is automatically removed or transformed, preventing hardware implementation of unnecessary logic
3Reliability
If manual checking of variable initialization is performed, then initialization correctness is improved, but time consumption and labor increase
Solution Approach 1:
The system automatically performs the checking and tracking of variable initialization status without requiring manual user intervention. The compiler/simulation tool autonomously monitors all variables and structures, ensuring initialization correctness while eliminating the time-consuming manual checking process
Solution Approach 2:
The system provides automatic feedback about the initialization status of variables and structures during compilation and simulation. This automated feedback mechanism allows designers to quickly identify and correct initialization issues without manual checking of thousands of design elements
Data Source
AI summary
A method and system are provided for automatically creating an implicit literal value in a user defined enumerated data type by inserting an additional literal value, scanning the HDL design files for broken interdependencies or potential incompatibilities with the implicitly defined literal value, and modifying the HDL design files to be in accordance with the implicitly defined literal value while maintaining the semantics of the VHDL language reference model.