Impure InP-on-Silicon Substrate for Large-Wafer Manufacturing
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Solution Overview
Problem
The limitations of using pure Indium Phosphide (InP) substrates in high-volume manufacturing due to their brittle nature and high wafer breakage during slicing, leading to expensive and low-yield fabrication processes for large-diameter wafers, which are necessary for cost-effective production.
Innovation Solution
The development of an impure Indium Phosphide (InP) semiconductor substrate comprising a silicon layer and an impure InP layer with controlled impurities, which is epitaxially grown or bonded to a silicon layer, providing structural strength and enabling the use of larger wafers without the limitations of pure InP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pure InP substrates are used, then electrical and thermal characteristics are improved, but structural strength deteriorates leading to high wafer breakage
Solution Approach 1:
The patent uses a composite structure consisting of a silicon layer and an impure InP layer. The silicon layer provides structural strength and mechanical stability, while the impure InP layer maintains desirable electrical and thermal characteristics. This composite approach resolves the contradiction by combining materials with complementary properties.
Solution Approach 2:
The patent changes the purity parameter of the InP layer from pure to impure (controlled impurities). This parameter change allows the InP layer to gain structural strength while retaining sufficient electrical and thermal performance for RF and photonic applications.
2Productivity
If large-diameter wafers are used, then productivity is improved, but manufacturing precision deteriorates due to high breakage rates
Solution Approach 1:
The silicon-InP composite structure enables the fabrication of large-diameter wafers (300mm and above) by providing the necessary structural strength during manufacturing processes. The silicon layer acts as a mechanical support that prevents wafer breakage during slicing, handling, and processing, thereby enabling high-volume manufacturing with acceptable yield.
3Reliability
If pure InP ingots are used, then electrical characteristics are improved, but ease of manufacture deteriorates due to brittleness
Solution Approach 1:
The patent deliberately introduces controlled impurities into the InP layer by changing the growth conditions (e.g., using Vapor Phase Epitaxy with specific precursor ratios). This parameter change makes the material easier to manufacture at scale while maintaining sufficient electrical characteristics for the intended applications.
Solution Approach 2:
The composite structure allows the use of impure InP that is easier to manufacture, while the silicon layer compensates for any minor deficiencies in electrical performance. This enables cost-effective fabrication processes with higher yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The impure InP substrate allows for the production of larger wafers with improved structural integrity and electrical/thermal characteristics, suitable for high-volume manufacturing and supporting heterojunction transistors, while reducing production costs and defects.
Implementation Method 1
The impure InP layer may be epitaxially grown on a Silicon nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Epitaxially growing the InP layer introduces impurities to the InP layer.
Data Source
AI summary
Aspects disclosed in the detailed description include an impure Indium Phosphide (InP) semiconductor substrate. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a semiconductor substrate comprising a silicon layer and an impure InP layer adjacent to the silicon layer. The impure InP layer may be epitaxially grown on a Silicon (Si) nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Utilizing an impure InP layer advantageously provides structural strength to be deployed in a 300 millimeter wafer process while achieving the electrical and thermal characteristic of InP it provides in a semiconductor substrate.