Impurity-Doped Dielectric Regions in 3D Memory
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Solution Overview
Problem
The increasing compactness of three-dimensional semiconductor devices leads to higher defect rates, hindering the achievement of increased integration density and improved distribution properties in semiconductor devices.
Innovation Solution
Incorporating a blocking dielectric with a stack structure containing an interlayer insulating layer and a gate electrode, along with lateral and lower impurity regions, particularly with carbon impurities, to enhance the semiconductor device's integration density and distribution properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the constituent elements of three-dimensional semiconductor devices are made more compact to increase integration density, then integration density is improved, but the defect rate increases
Solution Approach 1:
The patent introduces impurity regions with specific doping characteristics at critical boundary locations (between interlayer insulating layer and blocking dielectric, and between lower region and blocking dielectric). These localized impurity regions provide targeted electrical property modification to improve charge distribution and reduce defects in compact three-dimensional memory structures, thereby resolving the contradiction between high integration density and low defect rate
Solution Approach 2:
The patent modifies the electrical parameters of the semiconductor structure by introducing impurity regions with controlled doping concentrations and spatial distributions. This changes the charge carrier distribution and electrical field characteristics in the blocking dielectric regions, enabling improved reliability in compact three-dimensional devices without sacrificing integration density
2Stability of the object's composition
If impurity regions are added to improve distribution properties, then distribution properties are improved, but device complexity increases
Solution Approach 1:
The patent divides the impurity doping into distinct segmented regions: lateral impurity regions at the boundary between the interlayer insulating layer and blocking dielectric, and lower impurity regions at the boundary between the lower region and blocking dielectric. This segmentation allows independent optimization of charge distribution in different areas, improving overall distribution properties while maintaining a systematic and manageable device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves the integration density and distribution properties of semiconductor devices by reducing defect rates and enhancing the performance of the semiconductor device, specifically through the use of carbon impurity regions that improve the thickness distribution of the blocking dielectric.
Implementation Method 1
A lateral impurity region is provided, which is disposed within a boundary region between the interlayer insulating layer and the blocking dielectric. A lower impurity region is provided, which is disposed within a boundary region between the lower region and the blocking dielectric.
Implementation Method 2
a blocking dielectric disposed on a lower region, and a stack structure containing an interlayer insulating layer and a gate electrode facing the blocking dielectric
Data Source
AI summary
An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.