In-Chip Decoupling Capacitor Structural Test via Dummy Conductors
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Solution Overview
Problem
There is a lack of structural test coverage for in-chip decoupling capacitor circuits, leading to undetected defects such as shorts, which can cause functional failures over time and degrade the performance of the chip.
Innovation Solution
A structural test method and system that includes a circuit with dummy conductors connected to pull up and pull down points, and test logic to detect defects in passive logic components by sensing voltage changes across these points, providing comprehensive test coverage for on-chip decoupling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are placed on-chip to manage power supply noise, then power supply noise management is improved, but test coverage for structural defects is worsened
Solution Approach 1:
The patent introduces dummy conductors as intermediary elements connected to the decoupling capacitors. These dummy conductors serve as mediators that allow test logic to indirectly access and test the capacitors without interfering with their normal power supply noise management function. The dummy conductors are connected through pull-up and pull-down networks, creating a testing pathway that enables defect detection while preserving the original capacitor functionality.
2Measurement precision
If traditional testing methods are used for on-chip components, then active logic test coverage is maintained, but passive logic component defect detection is worsened
Solution Approach 1:
The patent segments the testing approach by creating separate dummy conductor networks specifically for passive logic component testing. Instead of using a unified testing method, the invention divides the test structure into distinct pull-up and pull-down networks with dedicated dummy conductors for each capacitor, enabling targeted testing of passive components without affecting active logic test coverage.
3Area of stationary object
If decoupling capacitors occupy significant chip area, then power supply noise management capability is improved, but defect detection capability is worsened
Solution Approach 1:
The patent adds a new dimensional aspect to the capacitor structure by introducing dummy conductors that extend from the capacitors to external test logic. This creates an additional testing dimension without increasing the physical footprint of the capacitors themselves. The dummy conductors provide a separate testing pathway that enables defect detection while maintaining the original capacitor area allocation for power supply noise management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively detects defects in passive logic components, including shorts, thereby enhancing the reliability and longevity of in-chip decoupling capacitor circuits and improving overall chip performance by ensuring timely identification and characterization of defects.
Implementation Method 1
test logic to detect defects associated with the plurality of passive logic components based on respective values of the pull up point and the pull down point
Data Source
AI summary
In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.